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DONE LED

When the configuration process successfully completes, the FPGA either actively drives the DONE pin High (DriveDone) or allows the DONE pin to float High using either an internal or external pull-up resistor, controlled by the DonePin bitstream generator option. To have DONE LED D1 lit after successful FPGA configuration, DriveDone and DonePin bitstream generator options for the DONE pin have to be set to have DONE actively driving its line (see Figure 56 and Table 32).
Figure 56: DriveDone and DonePin set to have DONE actively driving its line.
DriveDone defines whether the DONE pin is an active driver or an open-drain output.
DonePin defines whether or not the DONE pin has an internal pull-up resistor.

bitstream generator (BitGen) option

Setting

DriveDone

Yes

DonePin

Pullnone

Table 32: DriveDone and DonePin settings for having DONE actively driving its line.
See Xilinx UG332: Spartan-3 Generation Configuration User Guide (paragraph "DONE Pin") for additional information on these signals.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Startup Options > Drive Done Pin High > check the box
Generate Programming File > Process Properties > Configuration Options > Configuration Pin Done > float

Xilinx ISE Project Navigator option

setting

Drive Done Pin High

√ (checked)

Configuration Pin Done

Float

Table 33: Xilinx ISE Project Navigator settings for having DONE actively driving its line.
Consult ISE Help about the Process Properties of the Generate Programming File process in the Processes pane for additional information on these properties.

CCLK Frequency

In SPI Flash mode, the FPGA's internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM's Slave Clock input pin. The FPGA begins configuring using its lowest frequency setting. If so specified in the configuration bitstream, the FPGA increases the CCLK frequency to the specified setting for the remainder of the configuration process. The maximum frequency is specified using the ConfigRate bitstream generator option. The maximum frequency supported by the FPGA configuration logic depends on the timing for the SPI Flash device. For TE0320 SPI Flash PROM, use ConfigRate = 12 or lower.

This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:

Generate Programming File > Process Properties > Configuration Options > Configuration Rate > 12 (or lower)

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