Board revisions and assembly variants

To determine PCB revision and assembly variant from FPGA, TE0630 have dedicated user signals, which can be read by user core.
Board revision coded in 4 bits BR[3:0]

Table 12: Board revision pins
To define low (zero) level BR pin connected to ground rail, to define high (one) level BR pin left float (open). These pins should be configured with "pullup" option in user design.
See Table 12 for current list of board revisions.

Table 13: Board revisions
Module assembly variant encoded using AV[3:0] pins.

Table 14: Assembly variants pins
To define low (zero) level AV pin connected to ground rail through zero resistor, to define high (one) level AV pin left float (open). These pins should be configured with "pullup" option in user design.
Available module assembly variants listed in Table 15.

Table 15: Module assembly variants