Introduction
The reference architecture can be tested in two ways:
- USB communication tests + DMA tests
- full test (USB communication tests + DMA tests + other tests)
To test the USB communication in the Reference Architecture case is necessary
- to download the correct reference bitstream file in the FPGA and/or SPI Flash
- the USB FX2 microcontroller on the TE0300, TE0320 or TE0630 family should contain valid firmware;
- the host computer should have a specific driver installed;
- a USB cable should be used to connect the PC and the FPGA module
- run the C# or C++ Reference Project test
Full test (here)
To completely test the Reference Architecture is necessary
- to download the bitstream file (that create the Microblaze system) and the demo.elf file or to be certain that this two are already downloaded before;
- the USB FX2 microcontroller on the TE0300, TE0320 or TE0630 family should contain valid firmware;
- the host computer should have a specific driver installed;
- the host computer should have Xilinx EDK installed;
- a JTAG adapter cable. We recommend using the Xilinx Platform Cable USB (USB ↔ JTAG) .
- a USB cable should be used to connect the PC and the FPGA module (USB communication test)
The procedure is the following:
- update XPS project and download bitstream to the FPGA,
- check the fiirmware of FX2 microcontroler;
- run the demo project.
- USB communication tests + DMA tests
1) Update XPS project and download bitstream to the FPGA
Simple way:
Old version of Xilinx EDK
- Open the project by double-clicking on the system.xmp file. The Xilinx Platform Studio is opened.
- If you open the project with a new version of Xilinx XPS, the tool will try to update all the components of MicroBlaze system. In some case it is not possible to refuse the update.
- To compile the project press the "Download Bitstream to the FPGA" button.
- If the HDL design was successfully implemented and downloaded to the TE0300/TE0320/TE0630 family module, you can proceed to compile the MB software. Press the "build all user applications" button.
New version of Xilinx EDK (subdivision between XPS and SDK)
- Open the project by double-clicking on the system.xmp file. The Xilinx Platform Studio is opened.
- If you open the project with a new version of Xilinx XPS, the tool will try to update all the components of MicroBlaze system. In some case it is not possible to refuse the update.
- Select "Project" > "Select Elf Fle..."
- Select the Efl file demo.elf
- Select "Device Configuration" > "Update Bitstream"
- Select "Device Configuration" > "Download Bitstream"
- Configure Jtag_Uart using "Debug" > "Debug Configuration"
- Run XMD console using "Debug" > "Launch XMD"
- Run ClearTerminal Console
To compile the project you should first chose elf file
Long (clean) procedure
2) Check the fiirmware of FX2 microcontroler
The FX2 microcontroller on the TE0300, TE0320 or TE0630 family should contain valid firmware before proceeding.
- If the FX2 microcontroller has not been programmed before, please follow the instructions here and here. You can use Cypress, Python OpenFut or C# OpenFutNet programs.
- If you are sure that the FX2 microcontroller is properly connected, you can connect to the TE0300/TE0320/TE0630 module with a JTAG adapter cable. We recommend using the Xilinx Platform Cable USB.
- Then connect the TE0300/TE0320/TE0630 module to a USB cable.
???? If the HDL design was successfully implemented and downloaded to the TE0300/TE0320/TE0630 family module, you can proceed to compile the MB software. Press the "build all user applications" button. ??????
3) Run the demo project
Case A) Use the demo project with the XMD UART
With this application, you can test the PC ↔ USB ↔ JTAG ↔ FPGA communication using a simulated UART (XMD_UART) on JTAG/USB connection.
If you want to input some characters to the XMD UART, then open some terminal emulators,such as
- Microsoft / Hilgraeve HyperTerminal (usually included in Windows before Vista START MENU > All programs > Acessories > Communications > Hyper Terminal).
- ClearTerminal (very easy)
Connect using the following settings:
- No Host address
- Port Number: 4321
- TCP/IP connection type
The UART settings are:
- bits per seconds: 115,200
- data bits: 8
- parity: none
- stop bits: 1
- flow control: none (otherwise you will not be able to enter commands)
The UART port will output something of tis kind:
Before running the demo application, open the #project_root#\xmd.ini file:
1.rst
2.dow sw/test_hw.elf
3.#dow sw/demo.elf
4.run
5.terminal -jtag_uart_server 4321
To run the demo application
uncomment line 3 (remove "#")
comment line 2 (add "#" as first character)
save xmd.ini.
type "exit" in XMD command window
restart XMD by clicking again the "Start XMD" button in the XPS toolbar.
With this application, you can test the PC ↔ FPGA communication using a provided API.
If you want to input some characters to the XMD UART, then open some terminal emulators, such as Microsoft / Hilgraeve HyperTerminal (usually included in Windows START MENU / All programs / Acessories / Communications / Hyper Terminal). Connect using the following settings:
No Host address
Port Number: 4321
TCP/IP connection type
The UART settings are:
bits per seconds: 115,200
data bits: 8
parity: none
stop bits: 1
flow control: none (otherwise you will not be able to enter commands)
The UART port will output something of tis kind:
PLACEHOLDER STOP
Case B) Use the demo project without the XMD UART
To use the demo project without the XMD UART, you need to use "RS232" instead of "debug_module" as standard in/out port. Otherwise the application running on the Microblaze processor freezes if you disconnect the XMD. To accomplish that you need to set up the Microblaze "Software Platform Settings".
- In the dialog window select "OS and libraries" in the left window and pick "RS232" as a stdout and stdin interface.
- Then rebuild the software and download again the project to the FPGA.
The UART is then redirected to external pins, which are defined in the data/system.ucf file. The following snippet shows the case of the TE0300 series modules:
Module RS232 constraints*
Net fpga_0_RS232_RX_pin LOC=B13;
Net fpga_0_RS232_TX_pin LOC=B14;
Please refer to the table below for other module series relevant to this application note.
Sample UART to USB virtual COM port converter.
Sample UART to USB virtual COM port converter: signal detail.