The logic block XPS_I2C_SLAVE is a I2C communication core used for I2C communication between Xilinx FPGA's MicroBlaze soft processor and USB FX2 microcontroller. It is usually used for command, settings and status communication. The I2Cserial communication frequency is high speed (400 kHz).
With every Logical Architecture Layer (FPGA image) using MicroBlaze (with interrupt controller xps_intc configured to use xps_i2c_slave_0_IP2INTC_Irpt) and custom USB FX2 microcontroller's firmware:
With the Referece Architecture Layer (FPGA image) or compatible derived Logical Architecture Layer (FPGA image) using MicroBlaze and original (Trenz Electronic) USB FX2 microcontroller's firmware:
The XPS_I2C_SLAVE has 2 bus interfaces:
system.mhs extract
With every Logical Architecture Layer (FPGA image) using MicroBlaze (with interrupt controller xps_intc configured to use xps_i2c_slave_0_IP2INTC_Irpt) and custom USB FX2 microcontroller's firmware:
actually execute the delivered MB Command) using i2c_slave_int_handler() function in interrupt.c as start point;
With the Referece Architecture Layer (FPGA image) or compatible derived Logical Architecture Layer (FPGA image) using MicroBlaze and original (Trenz Electronic) USB FX2 microcontroller's firmware:
This way a safe bidirectional communication (through USB connection and USB FX2 microcontroller) between the FPGA microprocessor and computer is possible.
command Byte | Value | Description |
---|---|---|
0 SW:command[0] FW:EP1OUTBUF[0] | 0xAD | I2C_WRITE USB FX2 API command ID |
1 SW:command[1] FW:EP1OUTBUF[1] | 0x3F | I2C Address C_I2C_ADDRESS must be set properly for an I2C_SLAVE to be recognized by FX2. Address 63 (0x3F) is used in all reference designs. |
2 SW:command[2] FW:EP1OUTBUF[2] | 0x0C | FX2_Parameters.I2C_BYTES=0x0C of host software enum Number of bytes to write (max 32) |
3 SW:command[3] FW:EP1OUTBUF[3] | 0x00 | - |
4 SW:command[4] FW:EP1OUTBUF[4] | 0x00 | - |
5 SW:command[5] FW:EP1OUTBUF[5] | 0x00 | - |
6 SW:command[6] FW:EP1OUTBUF[6] | Command2MB | MB_Command ID to send to the MicroBlaze |
From 7 to 63 | - | Not used |
Command (aka host computer software's MB command to FPGA's MB2FX2_REGs) and reply (aka FPGA's MB2FX2_REGs to FX2 microcontroller firmware's autoresponse bytes array and host computer software's reply bytes array)
The host computer's software enable (sts_int_auto_configured=1) FX2 microcontroller's firmware to read MB2FX2_REGs; FX2 microcontroller's firmware reading of MB2FX2_REGs is enabled by host computer's software "Interrupt Pin polling" IntPinPool() in FW v3.01 or int_pin_pool() in FW v3.02 running in the superloop while(1) of fw.c).
or used with this command sets address and number of bytes to read from the I2C bus when an interrupt request (USB_INT) is received (in reference FX2 firmware v3.02 or v3.01, the interrupt request USB_INT is NOT served by an interrupt but by a normal functionSend the MB Command
(FX22MB_REG00 will be written as a result).The MicroBlaze execute this MB Command and writes data (Version Information of Reference Architecture running on the FPGA) to MB2FX2_REG0.
When MB write data to MB2FX2_REG0, the interrupt request pin INT0 (aka FPGA_INT0 in firmware files) is rised. This pin is connected to PA0/INT0 pin of FX2 microcontroller.
When the FX2 microcontroller's firmware read the rise of pin INT0 (=USB_INT=1 because MicroBlaze writes data to MB2FX2_REG0) it set the firmware variable FPGA_INT0 to 1.
If an autoresponse to interrupt request (USB_INT) is preconfigured (sts_int_auto_configured = 1) and FPGA_INT0=USB_INT=1, FX2 microcontroller firmware reads all MB2FX2 registers. The registers value are copied in the byte array auto_response_data by the "Interrupt Pin polling" int_pin_pool() firmware function (//"AUTORESPONSE: 2nd section to run" in the firmware code te_api.c).
Command (aka host computer software's MB command to FPGA's MB2FX2_REGs) with no reply.
For using the software header read comments in:
Feature/Description | Parameter Name | Allowable Values | Default Value | VHDL Type |
---|---|---|---|---|
System Parameters | ||||
target FPGA family s | C_FAMILY | partan3, spartan3e, spartan3a, spartan3adsp, spartan3an, virtex2p, virtex4, qvirtex4, qrvirtex4, virtex5 | virtex5 | string |
PLB Parameters | ||||
PLB base address | C_BASEADDR | Valid Address | None | std_logic_vector |
PLB high address | C_HIGHADDR | Valid Address | None | std_logic_vector |
PLB least significant address bus width | C_SPLB_AWIDT | 32 | 32 | integer |
PLB data width | C_SPLB_DWIDTH | 32, 64, 128 | 32 | integer |
Shared bus topology | C_SPLB_P2P | 0 = Shared bus topology | 0 | integer |
PLB master ID bus Width | C_SPLB_MID_WIDTH | log2(C_SPLB_NUM_ MASTERS) with a minimum value of | 1 | integer |
Number of PLB masters | C_SPLB_NUM_MASTER | 1-16 | 1 | integer |
Width of the slave data bus | C_SPLB_NATIVE_DWIDT | 32 | 32 | integer |
Burst support | C_SPLB_SUPPORT_BURSTS | 0 = No burst support | 0 | integer |
XPS_I2C_SLAVE Parameters | ||||
I2C slave address (1) | C_I2C_ADDRESS | 0-127 | 63 | integer |
Number of bytes to trigger IP2INTC_Irpt (2) | C_MB_INT_BYTE | 1-12 | 12 | integer |
Name | Interface | I/O | Initial State | Description |
---|---|---|---|---|
ChipScope[0:31] | - | O | - | Debug port |
USB_IFCLK | - | I | - | USB 48 MHz clock |
USB_INT | pin PA/INT0 of FX2 micontroller and FPGA chip | O | 0 | USB Interrupt request: interrupt request to USB FX2 microcontroller. In control of pin PA0/INT0, When the FX2 microcontroller's firmware read the rise of |
USB_SCL | - | I | - | USB I2C serial clock |
USB_SDA | - | I/O | - | USB I2C serial data I2Cserial communication frequency is high speed (400 kHz). |
IP2INTC_Irpt | xps_intc module of MicroBlaze | O | 0 | MB interrupt request: interrupt request to xps_i2c_slave_0_IP2INTC_Irpt signal. When the host sends a MB Command to the MicroBlaze (MB) |
OTHERS ARE PLBv4.6 SIGNALS | PLBv4.6 |
The logic block XPS_I2C_SLAVE has access to MicroBlaze functionality through a 6 × 32-bit memory mapped registers (3 for reading and 3 for writing, for a total of 12 bytes for reading and 12 bytes for writing) attached to PLBv4.6 bus:
The transactions of these connections are usually 12 bytes long (FX2_Parameters.I2C_BYTES=0x0C of host software enum; __xdata BYTE iar_count = 12 of firmware te_api.c; iar_count = EP1OUTBUF[2] of firmware te_api.c).
When an FPGA writes a word to the first register an interrupt request to the FX2 microcontroller is triggered/rised (USB_INT, pin INT0 is rised) . This pin INT0 is connected to PA0/INT0 pin of FX2 microcontroller. When an interrupt request is triggered the FX2 microcontroller automatically (a custom firmware that serves the interrupt request USB_INT with an ISR) or not (the reference firmware that use a not always enabled "Interrupt Pin polling" function in the while(1) superloop) reads the programmed number of bytes (usually 12) from the XPS_I2C_SLAVE MB2FX2 registers (MB2FX2_REGs). If the current Trenz Electronic reference FX2 microcontroller's firmware is used, the register value are "automatically" read if a autoresponse to interrupt request (USB_INT) is set ("Interrupt Pin polling" function enabled by an autoresponse flag setted by ). Otherwise the registers value are not automatically readed by FX2 microcontroller's firmware.
When the FX2 writes all 12 bytes to the FPGA registers (FX22MB_REGs) the Microblaze receives an interrupt (xps_i2c_slave_0_IP2INTC_Irpt) to know when the new data (MB Command for reference architecture case) was received. When the host sends a MB Command to the MicroBlaze (MB) soft embedded processor (FX22MB_REG0 will be written as a result), a MicroBlaze's interrupt (xps_i2c_slave_0_IP2INTC_Irpt) is rised and a FX2 interrupt handler (i2c_slave_int_handler() function in interrupt.c running on MicroBlaze) is called to actually execute the delivered MB Command.
Base Address + Offset (hex) | Register Name | Access Type | Default Value (hex) | Description |
---|---|---|---|---|
XPS FX2 IP Core Grouping | ||||
C_BASEADDR + 00 | MB2FX2_REG0 | R/W | 0x00000000 | Microblaze to FX2 register 0 |
C_BASEADDR + 04 | MB2FX2_REG1 | R/W | 0x00000000 | Microblaze to FX2 register 1 |
C_BASEADDR + 08 | MB2FX2_REG2 | R/W | 0x00000000 | Microblaze to FX2 register 2 |
C_BASEADDR + 0C | FX2MB_REG0 | Read | 0x00000000 | FX2 to Microblaze register 0 |
C_BASEADDR + 10 | FX2MB_REG1 | Read | 0x00000000 | FX2 to Microblaze register 1 |
C_BASEADDR + 14 | FX2MB_REG2 | Read | 0x00000000 | FX2 to Microblaze register 2 |
A single bit write to this register triggers interrupt to FX2 microcontroller (USB_INT => pin PA0/INT0 => FPGA_INT0 firmware variable).
When FX2 puts a last byte to this register an interrupt is triggered to microprocessor (IP2INTC_Irpt) if C_MB_INT_BYTES is set to 4.
When FX2 puts a last byte to this register an interrupt is triggered to microprocessor (IP2INTC_Irpt) if C_MB_INT_BYTES is set to 8.
When FX2 puts a last byte to this register an interrupt is triggered to microprocessor (IP2INTC_Irpt) if C_MB_INT_BYTES is set to 12.