PCN-20210127 TE0720 CPLD Firmware Revision Ugrade from REV05 to REV06

Products Affected

This change affects Trenz Electronic boards TE0720 of Revision 03: TE0720-03-*. See also Method of identification section below.

Changes

#1 Added generic options for PUDC and Boot Mode

Type: Enhancement
Reason: Provide easy option to select pullup/down for CPLD IO pins connected to Zynq Boot Mode and PUDC pins.
Impact: None. Default CPLD source code is still PUDC low (Zynq pullups activated) and Boot Mode QSPI/SD.

#2 Set pin associated with MIO7 to Pullnone

Type: Enhancement
Reason: Hardware pulldown on module installed for Zynq Bank0 voltage selection (3.3V). Further pulling unnecessary.
Impact: None.

#3 Adding internal 3.3V enable signal en_3v3_int

Type: Enhancement
Reason: Drive signals only high after core voltage is up.
Impact:  None, improved power sequencing.

#4 Set JTAG C_* signals high impedance until 3.3V is enabled

Type: Enhancement
Reason: JTAG pins connected to Zynq are high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#5 Boot mode pins set to GND or high impedance until en_3v3_int is high

Type: Enhancement
Reason: Boot Mode pins connected to Zynq should be high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#6 MIO14,15 high impedance until en_3v3_int is high

Type: Enhancement
Reason: UART pins connected to Zynq are high impedance as long as the core voltage is not available.
Impact: None, improved power sequencing.

#7 Improved JTAG time constraints

Type: Enhancement
Reason: Signal propagation constraints for JTAG were not implemented.
Impact: None, improved JTAG reliability at high speeds.

#8 JTAG drive strength adjustment

Type: Enhancement
Reason: Driver constraints adjusted for better signal integrity especially for high traffic.
Impact: None, improved JTAG connection.

#9 Bugfix I2C to GPIO module (I2C_to_GPIO.v)

Type: Bugfix
Reason: Communication with GPIO subsystem via I2C was not possible.
Impact:  Reading and writing data from/to CPLD internal registers via I2C bus works correctly.

#10 Changed Firmware Identifier to REV06

Type: Update
Reason: Show correct firmware revision with Trenz FSBL.
Impact: None. Actual firmware revision is shown with Trenz FSBL.

More information about System Controller can be found here: TE0720 System Controller. The new firmware is compatible with PCB revisions REV02 and REV03 of TE0720. Actual REV06 CPLD programming file of the Firmware is available in the Downolad area. The REV05 programming files are moved to the archive, available on the same Download area page.

Method of Identification

All TE0720-03 SoMs noted in the column replacement are delivered with REV06 CPLD firmware.

Production Shipment Schedule

TE0720-03-61C33FA variant will be available from mid of May in parallel to the precursor. From end of Juli 2021, after old stock is gone, all variants above are replaced by the corresponding variants.