AVN-22220322 TEBF0808 and TE080x Problems with PCIe

Description: 

From time to time there are problems with PCIe on some TEBF0808/TE080x combinations. The problem has various causes and is usually a combination of the following:

• 72992 - Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Possible link training failures or data errors on PCIe, SATA, or USB 3.0 protocol links using PS GTR
  • Xilinx provides patches for older Vivado Version, Vivado 2021.1 or newer should be fixed (Status 22.03.22 → Xilinx has changed this one time, so please check always AR#72992)
• TE080X PCIe Reference Clock initialisation will be done mostly via I2C on FSBL. Xilinx provide custom access on FSBL after MIO and GTR initialisation. PLL initialisation before GTR initialisation will improve the initialisation of the link
  • Trenz Electronic provides special FSBL inside Xilinx PSU (between MIO initialisation and GTR initialisation) to solve this problem. This will done since Vivado 18.3 reference design releases
• Alignment Problems with  SS5, ST5 connectors which can cause connection problems
  • Trenz Electronic has improved improved production to minimize tolerances.
  • Trenz Electronic starts to publish new Series TE081X which has same functionality but used ADM6 connectors which has very good selv alignment capabilities

Products Affected

This change affects all Trenz Electronic TEBF08x8 together with compatible SoMs: TE08xx.

Changes

#1

Type:

Reason: 

Impact:

Method of Identification

Production Shipment Schedule

From XXXXX, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

This PCN follows JEDEC Standard J-STD-046.