AVN-22220322 Problems with PCIe on TEBF0808 with TE080x

Description: 

From time to time there are problems with PCIe on some TEBF0808/TE080x combinations. The problem has various causes and is usually one or a combination of the following:

• 72992 - Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Possible link training failures or data errors on PCIe, SATA, or USB 3.0 protocol links using PS GTR
  • Xilinx provides patches for older Vivado Version, Vivado 2021.1 or newer should be fixed (Status 22.03.22 → Xilinx has changed this one time, so please check always AR#72992)
• TE080X PCIe Reference Clock initialisation will be done mostly via I2C on FSBL. Xilinx provide custom access on FSBL after MIO and GTR initialisation. PLL initialisation before GTR initialisation will improve the initialisation of the link
  • Trenz Electronic provides special FSBL inside Xilinx PSU (between MIO initialisation and GTR initialisation) to solve this problem. This will done since Vivado 18.3 reference design releases
• Alignment Problems with  SS5, ST5 connectors which can cause connection problems
  • Trenz Electronic has improved improved production to minimize tolerances.
  • Trenz Electronic starts to publish new Series TE081X which has same functionality but used ADM6 connectors which has very good self alignment capabilities
• PCIe Reference CLK can cause problem with PCIe
  • SoC/FPGA side: Xilinx GTR reference CLK support LVDS/LVPECL. PLL will be configured with correct LVDS standard on Trenz Reference Designs. In case of custom carrier and external reference clock, see also Xilinx ARx43641
  • PCIe Card side: PCIe requires HSCL IO or similar standard. Currently on the TEBF0808 AC coupled LVDS is used, which are generated by the PLLs of the modules. However, the PLLs (SI5338 of SI5345) also support HSCL. Better results are achieved when the PLL is changed to HSCL and the capacitors on the carrier are replaced by 0Ohm resistors.

Products Affected

This change affects all Trenz Electronic TEBF08x8 together with compatible SoMs: TE08xx.

Changes

#1

Type: Improvement

Reason: HSCL standard is more compline to PCIe specification and will improve PCIe stability. Changes will be implemented in newer reference designs (2021.2 or newer)

Impact: Carrier with still use AC coupled reference clk for PCIe, recommended to modify carrier, see #2

#2

Type: Improvement

Reason: DC coupled HSCL standard is more compline to PCIe specification and will improve PCIe Stability.  Capacitor C93 and C94 of PCI_REF_*/CLK0_* will be replaced with 0Ohm resistor

Impact: Carrier with still use AC coupled reference clk for PCIe, see #2

Method of Identification

Production Shipment Schedule

From XXXXX, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

This PCN follows JEDEC Standard J-STD-046.