| # | Change | Description/Reason |
|---|---|---|
| 1 | PS_CLK changed from 33.3333 to 50MHz | 50MHz is more reasonable if Zynq PS is operated in PLL bypass mode |
| 2 | 32MB winbond SPI changed to Spansion | 32Mbyte winbond is not supported in dual parallel mode |
| 3 | SPI flash size changed to 16MB per device | Xilinx FSBL does auto-disable linear mode if devices larger 16MB are detected |
| 4 | SPI package changed from BGA to SO8W | easier in manufacturing and and optical inspection |
| 5 | antenna select 0R from 0201 to 0402 | better for hand solder if need to change option after assembly |
| 6 | C29 to top layer and further away from conn | |
| 7 |
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