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PS Peripherals

 

MIO PinMapped toPull up/downNotes
0GPIOUpRTC Interrupt
1QSPI0  
2QSPI0Down 
3QSPI0Down 
4QSPI0DownOverride to up on base for bootmode change
5QSPI0Up 
6QSPI0Down 
7GPIODownOn-board LED
8CAN1 TXDDownCAN transceiver in SBC
9CAN1 RXD CAN transceiver in SBC
10SPI1 MOSI SBC SPI Bus
11SPI1 MISO SBC SPI Bus
12SPI1 SCLK SBC SPI Bus
13SPI1 SS0 SBC SPI Bus
14I2C0 SCL On-board RTC, and EEPROM
15I2C0 SDA  

Recommended Peripheral mapping for MIO Voltage bank 0.

 

PL Peripherals

Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's. PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

 

PS and PL Banks

BankVCCIOB2B I/O PinsNotes
5003.3V0 
501USER36Vref is connected to resistor divider to support HSTL18
13USER48Differential routing
333.3V33Single ended routing
343.3V0Ethernet PHY's
353.3V42Single ended routing

 

LED's

DesignatorColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenPL pin V18HighLVCMOS33

 

XADC Usage

 Connected toNotes
VP_0/VP_0SBC MUX_OUT 
AD0B2B 
AD1B2B 
AD3B2B 
AD4B2B 
AD5B2B 
AD7B2BOnly singled ended use, N input is GND
AD8B2B 
AD9B2B 
AD10B2B 
AD12B2B 
AD13B2B 
AD14B2B 
AD15B2B 

XADC is used with internal reference option.

Note the XADC capable pins are not routed differentially to the B2B connector. The performance and usability of the XADC must be evaluated.

 

 

 

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