| Top View | Bottom View |
PL Programmable Logic
TE0711 SoM is based on the Artix-7 Series Families FPGA and is available in five different logic densities (A15T,A35T,A50T,A75T,A100T).
The devices can be programmed with the free Xilinx Vivado WebPACK software. Further information on the Artix-7 FPGA can be found in the Xilinx document 7 Series FPGAs Overview (DS180).
| Board | FPGA | Logic Cells | Flip-Flops | BRAM |
|---|---|---|---|---|
| TE0711-01-15 | XC7A15T | 16,640 | 20,800 | 25 |
| TE0711-01-35 | XC7A35T | 33,280 | 41,600 | 50 |
| TE0711-01-50 | XC7A50T | 52,160 | 65,200 | 75 |
| TE0711-01-75 | XC7A75T | 75,520 | 94,400 | 105 |
| TE0711-01-100 | XC7A100T | 101,440 | 126,800 | 135 |
Configuration Modes
| Mode | Interface | Notes |
|---|---|---|
| JTAG | JTAG | For debugging purposes |
| SPI Flash | SPI Master | Main configuration mode. SPI Flash is used to store FPGA bitstream(s), PS Executable Object code and user data. |
TE0711 Configuration Modes
| Config Pin | Setting | Notes |
|---|---|---|
| M0 | 3.3V | Bootmode setting: Master SPI |
| M1 | 0V | |
| M2 | 0V | |
| CFGBVS | 3.3V | Select 3.3V as Config Bank I/O Voltage |
| PUDC | Strong pull-up to 3.3V | Pre-configuration pull-ups are DISABLED |
TE0711 Configuration pin settings
PS Processing System
TE0711 has no hard PS subsystem. Microblaze Soft Processor or Microblaze MCS can be used, they are both free of charge and included with Xilinx free Vivado Webpack version.
| Processor | Bus Interfaces | Peripherals |
|---|---|---|
| Microblaze MCS | Custom | UART, GPIO, Timer |
| Microblaze | AXI4, AXI4-Stream, LMB | Vivado IP Catalog |
Processing System Program Memory content can be embedded in the bitstream or loaded from SPI Flash by a bootloader.
Microblaze
Microblaze MCS
Example Microblaze MCS system, reset, clock, UART and LEDS to GPIO are connected by Vivado Board Part Interface wizard, no constraint files used or needed. This example Processing System uses less than 5% of A35T logic resources.
Clock Sources
| IC Designator | Description | Frequency | Used as | FPGA Pin | IO Standard | Vivado Board Part Interface |
|---|---|---|---|---|---|---|
| U3 | MEMS Oscillator | 12MHz | Clock for FT2232H | n/a | n/a | not available (no connection to FPGA) |
| U8 | MEMS Oscillator | 100MHz | System Clock | P17 | LVCMOS33 | System Clock |
In standard assembly option MEMS oscillator with 100MHz Frequency and 50 ppm stability is used. Other frequencies possible for custom order.
Reset Sources
| Reset Type | Source | Notes |
|---|---|---|
| Power On Reset | System Controller | PROG_B released after power on causing FPGA reconfiguration |
| B2B Reset | JM2.18 | Active low value forces FPGA reconfiguration |
| Dummy Reset | FPGA pin D9 | Can be used as reset with fixed always inactive value if needed (may have to add pullup or pulldown constraint) |
| Soft Reset | Any FPGA B2B I/O | User defined soft reset input with user defined polarity |
| Debug Reset | Microblaze MDM | JTAG debugger soft reset |
Dual channel USB UART/FIFO
TE0711 has on-board USB 2.0 High Speed UART/FIFO FT2232HQ from FTDI. Channel A can only be used in simple UART mode, Channel B can be used as UART, in 245 FIFO (Async) , JTAG (MPSSE) or High Speed Serial modes.
| FT2232H Pin | FPGA Pin | UART Mode | FIFO Mode | JTAG Mode | Fast Serial | comment |
|---|---|---|---|---|---|---|
Channel A (Vivado Board Part Interface name: "FTDI Channel A") | ||||||
| ADBUS0 | R11 | TXD | n/a | n/a | n/a | FT2232H UART TXD, connect to FPGA UART RXD input |
| ADBUS1 | L16 | RXD | n/a | n/a | n/a | FT2232H UART RXD, connect to FPGA UART TXD output |
| Channel B (Vivado Board Part Interface name: "FTDI Channel B") | ||||||
| BDBUS0 | P18 | TXD | D0 | TCK/SK | FSDI | UART: FT2232H UART TXD, connect to FPGA UART RXD input |
| BDBUS1 | R18 | RXD | D1 | TDI/DO | FSCLK | UART: FT2232H UART RXD, connect to FPGA UART TXD output |
| BDBUS2 | T18 | RTS | D2 | TDO/DI | FSDO | |
| BDBUS3 | U18 | CTSn | D3 | TMS/CS | FSCTS | |
| BDBUS4 | U17 | DTRn | D4 | GPIOL0 | - |
|
| BDBUS5 | T16 | DSRn | D5 | GPIOL1 | - | |
| BDBUS6 | V17 | DCDn | D6 | GPIOL2 | - | |
| BDBUS7 | U16 | RIn | D7 | GPIOL3 | - | |
| BCBUS0 | V16 | TXDEN | RXFn | GPIOH0 | - | |
| BCBUS1 | U14 | - | TXEn | GPIOH1 | - | |
| BCBUS2 | V15 | - | RDn | GPIOH2 | - | |
| BCBUS3 | T13 | RXLEDn | WRn | GPIOH3 | - | Active Low RX Activity LED in UART Mode |
| BCBUS4 | V14 | TXLEDn | SIWUB | GPIOH4 | SIWUB | Active Low TX Activity LED in UART Mode |
| BCBUS7 | U13 | PWRSAVn | PWRSAVn | GPIOH7 | PWRSAVn | |
FT2232H pin connection to FPGA I/O, all pins are connected to bank B14 with fixed 3.3V VCCIO and should be used with LVCMOS33 I/O Standard.
More information is available from FTDI website:
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