Overview
Trenz Electronic TE0711 (Rick Martin complete article number removed) is a FPGA module integrating a Xilinx Artix-7 SoM (System on Module), 32 Mbyte SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
All this on a tiny footprint, smaller than a credit card, at a competitive price.
Key Features
- Xilinx Artix-7 XC7A15T - XC7A100T (Rick Martin added range of FPGA)
- Rugged for shock and high vibration
- 32 Mbyte QSPI Flash memory
- 100 MHz MEMS oscillator
- Plug-on module with 2× 100-pin and 1× 60-pin high-speed hermaphroditic strips
- 178 FPGA I/Os (84 differential pairs) and available on board-to-board connectors
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- 3 user LEDs
- FTDI FT2232H USB2 High Speed IC Chip
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
Main Components
| Top View | Bottom View |
Artix-7 FPGA
32 Mbyte Quad SPI Flash memory
Dual USB to UART/FIFO Bridge (FT2232H)
System Controller CPLD
Oscillator 100MHz - System clock for FPGA
- EEPROM - for FT2232H
Oscillator 12MHz - for FT2232H
Detailed Description
PL Programmable Logic
TE0711 SoM is based on the Artix-7 Series Families FPGA and is available in five different logic densities (A15T,A35T,A50T,A75T,A100T).
The devices can be programmed with the free Xilinx Vivado WebPACK software. Further information on the Artix-7 FPGA can be found in the Xilinx document 7 Series FPGAs Overview (DS180).
| Board | FPGA | Logic Cells | Flip-Flops | BRAM |
|---|---|---|---|---|
| TE0711-01-15 | XC7A15T | 16,640 | 20,800 | 25 |
| TE0711-01-35 | XC7A35T | 33,280 | 41,600 | 50 |
| TE0711-01-50 | XC7A50T | 52,160 | 65,200 | 75 |
| TE0711-01-75 | XC7A75T | 75,520 | 94,400 | 105 |
| TE0711-01-100 | XC7A100T | 101,440 | 126,800 | 135 |
Configuration Modes
| Mode | Interface | Notes |
|---|---|---|
| JTAG | JTAG | For debugging purposes |
| SPI Flash | SPI Master 4-bit mode | Main configuration mode. SPI Flash is used to store FPGA bitstream(s), PS Executable Object code and user data. |
TE0711 Configuration Modes
| Config Pin | Setting | Notes |
|---|---|---|
| M0 | 3.3V | Bootmode setting: Master SPI |
| M1 | 0V | |
| M2 | 0V | |
| CFGBVS | 3.3V | Select 3.3V as Config Bank I/O Voltage |
| PUDC | Strong pull-up to 3.3V | Pre-configuration pull-ups are DISABLED |
TE0711 Configuration pin settings
Configuration Memory
TE0711 standard assembly option includes 32MByte SPI Flash for configuration and data storage. This memory is large enough to hold at least 4 uncompressed FPGA Bitstreams.
| Parameter | Value | Notes |
|---|---|---|
| Memory size (MBytes) | 32 | |
| Vendor | spansion | http://www.spansion.com |
| Device type | S25FL256SAGBHI20 | |
| Vivado CFGMEM | s25fl256sxxxxxx0-spi-x1_x2_x4 | Value to be used with Vivado labtools flash programmer |
| Vivado Board Part File Interface name | SPI Flash |
Parameter values for the SPI Flash memory included in the standard assembly option.
XADC
XADC is configured with internal reference voltage option. All XADC inputs that are shared with FPGA I/O are available in the B2B Connector. There is no access to the dedicated XADC input pins.
PS Processing System
TE0711 has no hard PS subsystem. Microblaze Soft Processor or Microblaze MCS can be used, they are both free of charge and included with Xilinx free Vivado Webpack version.
| Processor | Bus Interfaces | Peripherals |
|---|---|---|
| Microblaze MCS | Custom | UART, GPIO, Timer |
| Microblaze | AXI4, AXI4-Stream, LMB | Vivado IP Catalog |
Processing System Program Memory content can be embedded in the bitstream or loaded from SPI Flash by a bootloader.
Microblaze™
Microblaze MCS
Example Microblaze MCS system, reset, clock, UART and LEDS to GPIO are connected by Vivado Board Part Interface wizard, no constraint files used or needed. This example Processing System uses less than 5% of A35T logic resources.
Clock Sources
| IC Designator | Description | Frequency | Used as | FPGA Pin | IO Standard | Vivado Board Part Interface |
|---|---|---|---|---|---|---|
| U3 | MEMS Oscillator | 12MHz | Clock for FT2232H | n/a | n/a | not available (no connection to FPGA) |
| U8 | MEMS Oscillator | 100MHz | System Clock | P17 | LVCMOS33 | System Clock |
In standard assembly option MEMS oscillator with 100MHz Frequency and 50 ppm stability is used. Other frequencies possible for custom order.
Reset Sources
| Reset Type | Source | Notes |
|---|---|---|
| Power On Reset | System Controller | PROG_B released after power on causing FPGA reconfiguration |
| B2B Reset | JM2.18 | Active low value forces FPGA reconfiguration |
| Dummy Reset | FPGA pin D9 | Can be used as reset with fixed always inactive value if needed (may have to add pullup or pulldown constraint) |
| Soft Reset | Any FPGA B2B I/O | User defined soft reset input with user defined polarity |
| Debug Reset | Microblaze MDM | JTAG debugger soft reset |
LEDS
There are 3 LED's directly connected to FPGA I/O Pins. Vivado Board Part Interface (GPIO) name: "LEDS".
LED | Color | IOSTANDARD | FPGA Pin | Vivado Board Part name | GPIO Index" | Description |
|---|---|---|---|---|---|---|
| D1 | red | LVCMOS18 | A8 | "Module LEDS" : sys_led | 0 | User LED |
| D2 | green | LVCMOS33 | R17 | "Module LEDS" : led2 | 1 | User LED |
| D3 | green | LVCMOS33 | L15 | "Module LEDS" : led3 | 2 | User LED, active low |
Dual channel USB UART/FIFO
TE0711 has on-board USB 2.0 High Speed UART/FIFO FT2232HQ from FTDI. Channel A can only be used in simple UART mode, Channel B can be used as UART, in 245 FIFO, JTAG(MPSSE) or High Speed Serial modes. An standard 256 Byte EEPROM to store custom Configuration settings for FT2232H is available. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website.
| FT2232H Pin | FPGA Pin | UART Mode | FIFO Mode | JTAG Mode | Fast Serial | comment |
|---|---|---|---|---|---|---|
Channel A (Vivado Board Part Interface name: "FTDI Channel A") | ||||||
| ADBUS0 | R11 | TXD | n/a | n/a | n/a | FT2232H UART TXD, connect to FPGA UART RXD input |
| ADBUS1 | L16 | RXD | n/a | n/a | n/a | FT2232H UART RXD, connect to FPGA UART TXD output |
| Channel B (Vivado Board Part Interface name: "FTDI Channel B") | ||||||
| BDBUS0 | P18 | TXD | D0 | TCK/SK | FSDI | UART: FT2232H UART TXD, connect to FPGA UART RXD input |
| BDBUS1 | R18 | RXD | D1 | TDI/DO | FSCLK | UART: FT2232H UART RXD, connect to FPGA UART TXD output |
| BDBUS2 | T18 | RTS | D2 | TDO/DI | FSDO | |
| BDBUS3 | U18 | CTSn | D3 | TMS/CS | FSCTS | |
| BDBUS4 | U17 | DTRn | D4 | GPIOL0 | - |
|
| BDBUS5 | T16 | DSRn | D5 | GPIOL1 | - | |
| BDBUS6 | V17 | DCDn | D6 | GPIOL2 | - | |
| BDBUS7 | U16 | RIn | D7 | GPIOL3 | - | |
| BCBUS0 | V16 | TXDEN | RXFn | GPIOH0 | - | |
| BCBUS1 | U14 | - | TXEn | GPIOH1 | - | |
| BCBUS2 | V15 | - | RDn | GPIOH2 | - | |
| BCBUS3 | T13 | RXLEDn | WRn | GPIOH3 | - | Active Low RX Activity LED in UART Mode |
| BCBUS4 | V14 | TXLEDn | SIWUB | GPIOH4 | SIWUB | Active Low TX Activity LED in UART Mode |
| BCBUS7 | U13 | PWRSAVn | PWRSAVn | GPIOH7 | PWRSAVn | |
FT2232H pin connection to FPGA I/O, all pins are connected to bank B14 with fixed 3.3V VCCIO and should be used with LVCMOS33 I/O Standard.
More information is available from FTDI website:
Board-to-Board Connectors
View and download specifications of connectors used on this module here: Samtec LSHM
View and download the connector pinout for this module in the master pinout table here: Master Pinout Table
Initial Delivery state
| Storage device name | Content | Notes |
|---|---|---|
| FT2232H EEPROM | Empty, not programmed | |
| SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
| SPI Flash Quad Enable bit | Programmed | |
| SPI Flash main array | demo design | |
| EFUSE USER | Not programmed | |
| EFUSE Security | Not programmed |
Technical Specification
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
| Vin supply voltage | -0.3 | 6.0 | V | |
| 3.3V Vin supply voltage | -0.4 | 3.6 | V | |
| Storage Temperature | -40 | +100 | C |
Physical Dimensions
- Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
Download physical dimensions diagrams here: TE0711 Physical Dimensions
Power Supplies
| Vin | 3.3 V to 5.5 V | Typical 200mA, depending on customer design and connections |
| Vin 3.3V | 3.3 V | Typical 50mA, depending on customer design and connections |
For startup, a power supply with minimum current capability of 2A is recommended.
Vin and Vin 3.3V can be connected to the same source (3.3 V).
| Commercial grade modules | 0 °C to +70 °C |
| Industrial grade modules | -40 °C to +85 °C |
Depending on the customer design, additional cooling might be required.
Weight
| TBDg | Without bolts |
| TBDg | With bolts screwed to the module |
Downloads For This Product
Recommended Software: Xilinx Vivado WebPACK (free license)
A15T, A35T, A50T, A75T are not supported by Xilinx legacy tools (ISE, Impact).
The schematic is available for download here: TE0711 Schematic
Resources
Disclaimer
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