The customizable IBERT core for 7 series FPGA can be used for evaluating and monitoring the GTs.
The IBERT core can be defined and generated using the Vivado built-in IP Cores. And with the generated example designs the IBERT Test can be implemented.
|GT Clock Location||GT Clock(MHz)||Notes|
|TE0712||Quad_216 CLK0||125||Si5338 Clock is connected to GT CLK2 input|
|TE0715||Quad_112 CLK1||125||Si5338 Clock is connected to GT CLK2 input|
|TE0741||Quad_115 CLK1, Quad_116 CLK1||125||Si5338 Clock is connected to GT CLK1 input|
Step to Step to generate the IBERT core:
- Create a new IP Location.
- Double-click IBERT 7 series GTP (or GTX).
- Define the new IBERT. Set the LineRate, select the DataWidth, the Quad count, the Refclk and the Clock Source.
- Generate the Core.
- Right-click the IP in the Sources view, choose "Open IP Example Design".
- A new project with the IBERT example design will be created and opened.
- Generate Bitstream. Open and view the completed design.
- Testing with Hardware
- LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTP Transceivers v3.0 (pg133)
- LogiCORE IP Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers v3.0 (pg132 )