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Overview

Firmware for PCB CPLD with designator U2. CPLD Device in Chain: LCMX02-256HC

Feature Summary

  • Power Management

  • JTAG

  • Boot Mode

  • LED

  • I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name

Direction

Pin

Pullup/Down

Bank Power

Description

BOOTMODE_1

out

21

None

LVCMOS18

Boot Mode Pin, connected to Zynq MIO5 (U1)

EN_PL

out

23

Up

LVCMOS33

Enable PL Power, connected to U4

F_TMS

out

9

Up

LVCMOS18

JTAG chain to Zynq TMS (W11/U1), just pass through from TMS

SLEWRATE=FAST DRIVE=8

F_TCK

out

8

Up

LVCMOS18

JTAG chain to Zynq TCK (W12/U1), just pass through from TCK

SLEWRATE=FAST DRIVE=8

F_TDI

out

10

Up

LVCMOS18

JTAG chain to Zynq TDI (V11/U1), just pass through from TDI

SLEWRATE=FAST DRIVE=8

F_TDO

in

11

None

LVCMOS18

JTAG chain to Zynq TDO (W10/U1), just pass through from TDO, maxdelay 10ns

I2C_SCL

in

17

None

LVCMOS18

I2C Bus from SoC

I2C_SDA

inout

16

None

LVCMOS18

I2C Bus from SoC

JTAG_EN

in

26

-

VCCIO 3.3 V

Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)

MIO0

in

14

Up

LVCMOS18

sd card detection signal coming from connected B2B, also connected to Zynq.
Depending on the firmware used, the extended boot mode JTAG can be set.

Default: Only SD/QSPI Boot mode possible

MIO8

in

13

Up

LVCMOS18

external pullup, for status of 'qspi_fbclk' from Zynq

PS_SRST

in

12

Up

LVCMOS18

system reset signal coming from connected B2B, also connected to Zynq.

PWR_PL_OK

in

27

Up

LVCMOS33

power good for PL

PWR_PS_OK

in

28

Up

LVCMOS33

power good for PS

RST_IN_N

in

25

None

LVCMOS18

Main Reset to U41 (PS_1.8V) coming from connected B2B

RTC_INT

in

4

None

LVCMOS33

RTC output interrupt signal

Serial number

-

20

-

-

no function, not used

TMS

in

29

Up

LVCMOS33

JTAG coming from connected B2B, maxdelay 10ns

TCK

in

30

Up

LVCMOS33

JTAG coming from connected B2B, maxdelay 10ns

TDI

in

32

Up

LVCMOS33

JTAG coming from connected B2B, maxdelay 10ns

TDO

out

1

None

LVCMOS33

JTAG coming from connected B2B

LED

out

5

None

LVCMOS33

used as status LED, connected to green LED (D1); SLEWRATE=SLOW

 

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between the CPLD and FPGA is realised by JTAG_EN (logical one for CPLD, logical zero for FPGA) on B2B J1-148 (JTAG_EN).

Boot Mode

The adjustable Boot Mode is depending on programmed firmware.

Default (for Boot mode QSPI/SD):

BOOTMODE_1 is set constant to 1. Boot mode can be changed between QSPI or SD with B2B J2-133 Pin (BOOTMODE/ Zynq (MIO4)). 

Boot mode

MIO5

(BOOTMODE_1 from CPLD)

MIO4

(BOOTMODE from B2B J2-133)

QSPI

1

0

SD

1

1

Optional (for Boot mode QSPI/SD/JTAG):

BOOTMODE_1 depends on MIO0 (sd card detection) connected to B2B J2-137 Pin (SD card detection/ Zynq (MIO0))

  • sd card detected --> SD/QSPI boot mode
  • no sd card detected --> JTAG/NA boot mode

Boot mode

MIO5

(BOOTMODE_1 from CPLD)

MIO4

(BOOTMODE from B2B J2-133)

comments
JTAG00SD card is not allowed to be inserted
NA01not supported boot mode!

QSPI

1

0

inserted SD card is required

SD

1

1

inserted SD card is required

I2C interface

The CPLD firmware consists of an i2c-to-GPIO block. This subsystem provides an i2c protocol interface with several 8-bit registers (GPIO_input[8*i+7:8*i]) for reading from the CPLD as parallel general purpose inputs (I/Os). The read data is transferred to the FPGA via the i2c bus interface protocol. The chip address of this block in the firmware is 0x30, "i" is the data address in this case. The associated i2c bus is bus 1.

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read:

Read RegisterAddresscommand in linux consolerelated dataDefaultDescription
GPIO_input[7:0]0x00i2cget -y 1 0x30 0x00BOOTMODE_VAR (8 bits)0x01

Bootmode variants (depending on firmware):

  • 1 = QSPI/SD (default)
  • 2 = QSPI/SD/(NAND*)/JTAG

*no NAND flash present

GPIO_input[15:8]0x01i2cget -y 1 0x30 0x01DEB_FREQ0x20

system clock frequency in Hz for debounce.

Default: 24.18MHz (Little-Endian)

GPIO_input[23:16]0x02i2cget -y 1 0x30 0x02DEB_FREQ0xf5
GPIO_input[31:24]0x03i2cget -y 1 0x30 0x03DEB_FREQ0x70
GPIO_input[39:32]0x04i2cget -y 1 0x30 0x04DEB_FREQ0x01
GPIO_input[47:40]0x05i2cget -y 1 0x30 0x05DEB_STABLE_TIME (8 bits)0x0adebounce input signal must remain stable in ms
GPIO_input[55:48]0x06i2cget -y 1 0x30 0x06I2C_slave_addr (8 bits)0x30I2C slave address
GPIO_input[63:56]0x07i2cget -y 1 0x30 0x07I2C_if_type (8 bits)0x00

I2C interface type

  • 0 = Master
  • 1 = Slave
GPIO_input[71:64]0x08i2cget -y 1 0x30 0x08I2C_rd_type (8 bits)0x00

I2C read type

  • 0 = At
  • 1 = Before
GPIO_input[79:72]0x09i2cget -y 1 0x30 0x09I2C_addr_bits (8 bits)0x08I2C address bits
GPIO_input[87:80]0x0ai2cget -y 1 0x30 0x0aCPLD_REVISION (8 bits)0x02CPLD revision
GPIO_input[95:88]0x0bi2cget -y 1 0x30 0x0bPCB_REVISION (8 bits)0x02PCB revision
GPIO_input[103:96]0x0ci2cget -y 1 0x30 0x0c

GPIO_input(96)   = PWR_PL_OK
GPIO_input(97)   = PWR_PS_OK
GPIO_input(98)   = MIO0
GPIO_input(99)   = MIO8
GPIO_input(100) = RTC_INT
GPIO_input(101) = RST_IN_N
GPIO_input(102) = PS_SRST
GPIO_input(103) = '0'

0x63/
0x67

Status of defined CPLD input signals

  • PWR_PL_OK (Pin 27)
  • PWR_PS_OK (Pin 28)
  • MIO0 (Pin 14)
  • MIO8 (Pin 13)
  • RTC_INT (Pin 4)
  • RST_IN_N (Pin 25)
  • PS_SRST (Pin 12)

Default:

  • 0x63 with SD card
  • 0x67 without SD card

Power

PL Power is enabled.

LED

LED glows depending on input signals 'RST_IN', 'PS_SRST' or' MIO8'

StatusDescription
ONif RST_IN or PS_SRST or MIO8 is zero
Blinkingall other states

Appx. A: Change History and Legal Notices

Revision Changes

REV01 to REV02

  • added I2C interface
  • defined generic parameter
  • new Boot Mode variants (depending on firmware)

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescriptionFirmware release

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 REV02REV02, REV01

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REV02 documentation update2023-02-07
2018-03-08v.3REV01REV01,
REV02
John HartfielREV01 documentation update2016-05-30

All

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Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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