- Created by Mohsen Chamanbaz, last modified on 06 03, 2024
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Overview
CPLD Device with designator U5: LCMX02-1200HC.
Feature Summary
- JTAG
- UART
- I2C
- Power
- Boot Mode
- Reset
- SD
- LED
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
---|---|---|---|---|---|
UART_TXD | in | 77 | NONE | 3.3V | UART0 TX / Sends data to MIO13. MIO13 is connected to B2B JB1 Pin 98. ( HSS console ) |
UART_RXD | out | 84 | NONE | 3.3V | UART0 RX / Recieves data from MIO12. MIO12 is connected to B2B JB1 Pin 100. ( HSS console ) |
CM0 | in | 76 | UP | 3.3V | DIP switch S2-2 / used as JTAG Selection/ If CM0 set to high (S2-2 OFF) → Access to CPLD of module otherwise access to FPGA of module. |
CM1 | in | 75 | UP | 3.3V | DIP switch S2-1 / Used to change PGOOD pin state /If CM1 set to high (S2-1 OFF) → PGOOD = '1' otherwise '0' |
EN1 | out | 81 | NONE | 3.3V | B2B Power Enable |
FL_0 | inout | 28 | NONE | 3.3V | LED (D3-red) / Status |
FL_1 | inout | 27 | NONE | 3.3V | LED (D4-green) / Status |
FT_B_RX | out | 138 | NONE | 3.3V | FTDI UART RX (UART1 RX) |
FT_B_TX / BDBUS0 | in | 139 | UP | 3.3V | FTDI UART TX (UART1 TX) |
JTAGEN | --- | 120 | --- | 3.3V | Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3 |
M_TCK | in | 131 | NONE | 3.3V | JTAG from/to FTDI |
M_TDI | in | 136 | NONE | 3.3V | JTAG from/to FTDI |
M_TDO | out | 137 | NONE | 3.3V | JTAG from/to FTDI |
M_TMS | in | 130 | NONE | 3.3V | JTAG from/to FTDI |
MIO0 | in | 94 | UP | 3.3V | DIP-S4 and B2B JB1 Pin 88. This signal is connected to MODE signal. |
MIO12 | in | 100 | NONE | 3.3V | Sends data to UART_RX |
MIO13 | out | 99 | NONE | 3.3V | Read data from UART_TX |
MIO14 | out | 105 | NONE | 3.3V | Receives data from FT_B_TX of FTDI chip |
MIO15 | in | 95 | NONE | 3.3V | Sends data to FT_B_RX of FTDI chip |
MIO9 | out | 96 | NONE | 3.3V | SD_CD signal is directed to this signal in firmware. |
MODE | out | 83 | NONE | 3.3V | Dip switch S2-4 is connected to MODE pin ( B2B-JB1-31) |
NOSEQ | inout | 78 | UP | 3.3V | NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux. |
PGOOD | inout | 82 | UP | 3.3V | PGOOD can be set or reset via CM1 ( dip switch S2-1) |
PHY_LED1 | out | 86 | DOWN | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED1R | out | 92 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED2 | out | 85 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PHY_LED2R | out | 91 | NONE | 3.3V | Shows the status of PGOOD, CM0 or MIO0 signals. |
PROGMODE | out | 104 | UP | 3.3V | Enable B2B Module JTAG access to CPLD for Firmware update |
RESIN | out | 119 | NONE | 3.3V | Module Reset Pin on B2B connector |
S1 | in | 114 | UP | 3.3V | Push Button / Used as module Reset |
SD_CD | in | 93 | UP | 3.3V | Forwarded to MIO9 |
SD_SEL | out | 113 | NONE | 3.3V | Set to GND / currently_not_used |
TCK_B | out | 1 | NONE | 3.3V | JTAG from/to Module |
TDI_B | out | 3 | NONE | 3.3V | JTAG from/to Module |
TDO_B / C_TDO | in | 2 | UP | 3.3V | JTAG from/to Module |
TMS_B | out | 4 | NONE | 3.3V | JTAG from/to Module |
ULED1 | out | 117 | NONE | 3.3V | LED (D1-red) / Shows the status of PGOOD, CM0 or shows the UART1 RX. |
ULED2 | out | 115 | NONE | 3.3V | LED (D2-green) / Shows the status of PGOOD, CM0 or shows the UART1 TX. |
X16 | in | 59 | UP | 3.3V | currently_not_used |
X17 | out | 60 | NONE | 3.3V | currently_not_used |
SDA / MIO11 | inout | 97 | UP | 3.3V | I2C Data |
SCL /MIO10 | in | 98 | UP | 3.3V | I2C Clock (100kHz) |
Functional Description
Dip Switch
DIP Switch S2 | ||||
---|---|---|---|---|
S2-1 | S2-2 | S2-3 | S2-4 | Description |
CM1 | CM0 | JTAGEN | MIO0 | JTAGEN set carrier board CPLD into the chain for firmware update. |
JTAG
JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module). TEB2000 CPLD can be selected with JTAGEN (DIP-S2-3). Module FPGA/CPLD access can be switched with PROGMODE which is driven by CM0 (DIP-S2-2). CM1 and CM0 are pulled up in CPLD.
S2-2 | S2-3 | CM0 (PROGMODE) (S2-2) | JTAGEN (S2-3) | Description |
---|---|---|---|---|
OFF | OFF | 1 | 1 | Access to TEB2000 CPLD |
OFF | ON | 1 | 0 | Access to CPLD of B2B Module |
ON | OFF | 0 | 1 | Access to TEB2000 CPLD |
ON | ON | 0 | 0 | Access to FPGA of B2B Module |
Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.
EN1
EN1 is set to one.
NOSEQ
NOSEQ pulled up to 3.3V. NOSEQ can be set or reset by i2c interface in linux console, if an i2c interface is prepared for this in linux.
NOSEQ | Connected to | Related command in linux console | Description |
---|---|---|---|
'0' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x00 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x00 |
'1' | GPIO_output[16] | i2cset -y <related bus> 0x20 0x02 0x01 | It is depends on the linux design. For example → i2cset -y 0 0x20 0x02 0x01 |
To read the NOSEQ status, GPIO_input[16] must be read like the following instruction:
i2cget -y <related bus> 0x20 0x02
For example --> i2cget -y 0 0x20 0x02
PGOOD
PGOOD pulled up to 3.3V. PGOOD pin can be set or reset by user. If CM1 set to high (S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.
PGOOD | Condition | Description |
---|---|---|
'0' | CM1 = '0' | Dip switch S2-1 ON |
'1' | CM1 = '1' | Dip switch S2-1 OFF |
Reset
RESIN is driven by S1 (Push Button). Button is debounced.
Pin | CPLD Pin | Connected to | Description |
---|---|---|---|
RESIN | 119 | B2B JB2 Pin 17 | Active-low |
Boot Mode
MODE pin is sourced by MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP. PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:
S2-1 | S2-4 | PGOOD | MIO0 | Description |
---|---|---|---|---|
ON | ON | 0 | 0 | JTAG boot mode |
OFF | ON | 1 | 0 | SD Card boot mode, PHY LEDs glow orange |
OFF | OFF | 1 | 1 | QSPI boot mode, PHY LEDs glow green |
UART
MIO14 is driven by BDBUS0 (FTDI RX). BDBUS1 (FTDI TX) is driven by MIO15 . MIO13 is driven by UART_TXD. UART_RXD is driven by MIO12.
UART 0 (HSS Console) | ||||||
---|---|---|---|---|---|---|
CPLD UART Input Pin | CPLD Pin | Connected to | CPLD UART Output Pin | CPLD Pin | Connected to | Description |
MIO12 | 100 | B2B-JB1-100 | UART_RXD | 84 | U8-Pin 11 | |
UART_TXD | 77 | U8-Pin 13 | MIO13 | 99 | B2B-JB1-98 | |
UART 1 (Linux Console) | ||||||
CPLD UART Input Pin | CPLD Pin | Connected to | CPLD UART Output Pin | CPLD Pin | Connected to | Description |
FT_B_TX | 139 | FTDI Chip U4 Pin 32 | MIO14 | 105 | B2B-JB1-91 | |
MIO15 | 95 | B2B-JB1-86 | FT_B_RX | 138 | FTDI Chip U4 Pin 33 |
SD
SD selection is set to GND (SD Card slot). MIO9 is switched to SD_CD and its status depends on SD_CD .
On-board LEDs
RJ45 Connector LED | Designator | LED Status | Condition | Description |
---|---|---|---|---|
PHY_LED1 (Green LED Anode, Yellow LED Cathode) PHY_LED1R (Green LED Cathode, Yellow LED Anode) | J14B | Fast blink yellow | PGOOD = '0' | |
Slow blink yellow green | CM0='1' → Access to CPLD of Module | |||
Green | MIO0 = '1' | |||
yellow | MIO0 = '0' | |||
PHY_LED2 (Green LED Cathode, Yellow LED Anode) PHY_LED2R (Green LED Anode, Yellow LED Cathode) | J14C | Fast blink yellow | PGOOD = '0' | |
Slow blink yellow green | CM0='1' → Access to CPLD of Module | |||
Green | MIO0 = '1' | |||
yellow | MIO0 = '0' |
LED | Designator | LED Status | Condition | Description |
---|---|---|---|---|
ULED1 (Red) | D1 | Blink, if Power Good is low | ||
ON | ||||
FTDI UART RX | ||||
ULED2 (Green) | D2 | Blink, if Power Good is low | ||
ON | ||||
FTDI UART TX | ||||
FL_0 (Red) | D3 | OFF | ||
ON | ||||
User defined with B2B Pin JB2-99 | ||||
FL_1 (Green) | D4 | OFF | ||
ON | ||||
User defined with B2B Pin JB2-90 |
I2C to GPIO
I2C to GPIO is a subsystem in firmware of CPLD that provides an i2c interface that writes received data to GPIO_output 8 bit registers or reads 8 bit GPIO_input registers and send read data to i2c bus.
I2C bus is connected to MIO10 ( SCL signal) and MIO11 (SDA signal). MIO10 to MIO15 are direct connection between CPLD of TEB2000 and FPGA on the module (for example TEM0007) through B2B connector. If in FPGA design exists no i2c interface for MIO10 and MIO11, this block will be unused. More information about MIO10 to MIO15 are shown in the following table for TEM0007 modules and TEB2000 carrier board:
B2B Pin | B2B JB1-96 | B2B JB1-94 | B2B JB1-100 | B2B JB1-98 | B2B JB1-91 | B2B JB1-86 | |
---|---|---|---|---|---|---|---|
Carrier board | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Label / Firmware function | Description |
TEB2000 | MIO10 / I2C-SCL | MIO11 / I2C-SDA | MIO12 / GPIO | MIO13 / GPIO | MIO14 / UART0-RX | MIO15 / USRT0-TX | MIO10 and MIO11 are used in CPLD firmware as I2C SCL and SDA respectively. |
B2B Pin | B2B JM1-95 | B2B JM1-93 | B2B JM1-99 | B2B JM1-97 | B2B JM1-92 | B2B JM1-85 | |
Module | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Label / Chip pin | Description |
TEM0007 | I2C_CON_SCL / A3 | I2C_CON_SDA / E3 | UART_CON_TX / C2 | USRT_CON_RX / D3 | UART_RX / H2 | UART_TX / H5 | MIO10 and MIO11 are already set in test_design of |
There are more additional connections between CPLD and FPGA on the module , that are listed in the following table:
CPLD Pin | Carrier board B2B Pin | Module B2B Pin | In firmware used as | Description |
---|---|---|---|---|
X6 | B2B JB1-84 | B2B JM1-83 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(31) ) |
Y0 | B2B JB2-76 | B2B JM2-75 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(24) ) |
Y1 | B2B JB2-78 | B2B JM2-77 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(25) ) |
Y2 | B2B JB2-82 | B2B JM2-81 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(26) ) |
Y3 | B2B JB2-84 | B2B JM2-83 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(27) ) |
Y4 | B2B JB2-86 | B2B JM2-85 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(28) ) |
Y5 | B2B JB2-88 | B2B JM2-87 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(29) ) |
Y6 | B2B JB2-90 | B2B JM2-89 | No specific function. It can only be read by GPIO_input. | It can be read via i2c to GPIO. ( GPIO_input(30) ) |
I2C to GPIO registers access methods
I2C to GPIO subsystem has 4 output and 4 input 8 bit registers. These registers can be written or read in linux as shown in the following tables:
GPIO input register | Address | Read command in Linux | Description |
---|---|---|---|
GPIO_input[7:0] | 0x00 | i2cget -y 0 0x20 0x00 | 0x20 is device address. ( I2C to GPIO address). |
GPIO_input[15:8] | 0x01 | i2cget -y 0 0x20 0x01 | 0x20 is device address. ( I2C to GPIO address). |
GPIO_input[23:16] | 0x02 | i2cget -y 0 0x20 0x02 | 0x20 is device address. ( I2C to GPIO address). |
GPIO_input[31:24] | 0x03 | i2cget -y 0 0x20 0x03 | 0x20 is device address. ( I2C to GPIO address). |
GPIO output register | Address | Write command in Linux | Description |
---|---|---|---|
GPIO_output[7:0] | 0x00 | i2cset -y 0 0x20 0x00 <data> | 0x20 is device address. ( I2C to GPIO address). 0x00 is register address. |
GPIO_output[15:8] | 0x01 | i2cset -y 0 0x20 0x01 <data> | 0x20 is device address. ( I2C to GPIO address). 0x01 is register address. |
GPIO_output[23:16] | 0x02 | i2cset -y 0 0x20 0x02 <data> | 0x20 is device address. ( I2C to GPIO address). 0x02 is register address. |
GPIO_output[31:24] | 0x03 | i2cset -y 0 0x20 0x03 <data> | 0x20 is device address. ( I2C to GPIO address). 0x03 is register address. |
I2C to GPIO registers
GPIO input registers
The following port or signals can be read via GPIO_input[ ] registers.
GPIO input bit | Port/Signal | Description |
---|---|---|
0 | CPLD_REVISION [0] | |
1 | CPLD_REVISION [1] | |
2 | CPLD_REVISION [2] | |
3 | CPLD_REVISION [3] | |
4 | CPLD_REVISION [4] | |
5 | CPLD_REVISION [5] | |
6 | CPLD_REVISION [6] | |
7 | CPLD_REVISION [7] |
GPIO input bit | Port/Signal | Description |
---|---|---|
8 | X0 | |
9 | X1 | |
10 | X2 | |
11 | X3 | |
12 | X4 | |
13 | X5 | |
14 | X6 | |
15 | X7 |
GPIO input bit | Port/Signal | Description |
---|---|---|
16 | NOSEQ | |
17 | X8 | |
18 | X9 | |
19 | X10 | |
20 | X11 | |
21 | X12 | |
22 | X13 | |
23 | X14 |
GPIO input bit | Port/Signal | Description |
---|---|---|
24 | X15 | |
25 | X16 | |
26 | X17 | |
27 | CM0 | |
28 | CM1 | |
29 | PGOOD | |
30 | S1 | |
31 | USB_OC |
GPIO output registers
The following port or signals can be written via GPIO_output[ ] registers.
GPIO output bit | Port/Signal | Description |
---|---|---|
0 | Reserved | |
1 | Reserved | |
2 | Reserved | |
3 | Reserved | |
4 | Reserved | |
5 | Reserved | |
6 | Reserved | |
7 | Reserved |
GPIO output bit | Port/Signal | Description |
---|---|---|
8 | X0 | |
9 | X1 | |
10 | X2 | |
11 | X3 | |
12 | X4 | |
13 | X5 | |
14 | X6 | |
15 | X7 |
GPIO output bit | Port/Signal | Description |
---|---|---|
16 | NOSEQ | |
17 | X8 | |
18 | X9 | |
19 | X10 | |
20 | X11 | |
21 | X12 | |
22 | X13 | |
23 | X14 |
GPIO output bit | Port/Signal | Description |
---|---|---|
24 | X15 | |
25 | X16 | |
26 | X17 | |
27 | Reserved | |
28 | Reserved | |
29 | Reserved | |
30 | Reserved | |
31 | Reserved |
Appx. A: Change History and Legal Notices
Revision Changes
- REV01
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
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Appx. B: Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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