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Overview

The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020).

This SoM has following peripherals on board:

  • 1 x Gbps Ethernet Phy transceiver
  • 2 x 100 Mbps Ethernet PHY transceivers
  • 512 MByte DDR3 SDRAM
  • 32 MByte Flash-Memory
  • 4 Gbyte e-NAND-Flash-Memory
  •  USB PHY transceiver
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

All modules in 4 x 5 cm form factor are mechanically compatible.

Block diagram

Board Components

Main Components:

Key Features

  • Industrial-grade Xilinx Zynq-7000 (XC7Z020) SoM
  • Rugged for shock and high vibration
  • 2 x ARM Cortex-A9
  • 1 x 10/100/1000 Mbps Ethernet transceiver PHY
  • 2 x 10/100 Mbps Ethernet transceiver PHYs
  • 3 x MAC-Address EEPROMs
  • 16-Bit wide 512 MByte DDR3 SDRAM
  • 32 MByte QSPI-Flash-Memory
  • 4 GByte e-NAND-Flash-Memory (embedded eMMC Memory)
  • USB 2.0 high-speed ULPI transceiver
  • Plug-on module with 2 x 120-pin high-speed hermaphroditic strips
  • 136 FPGA I/Os (58 LVDS pairs possible) and 6 PS MIOs available on board-to-board connectors
  • On-board high-efficiency DC-DC converters
    • 4.0 A x 1.0 V power rail
    • 1.5 A x 1.5 V power rail
    • 1.5 A x 1.8 V power rail
    • 1.5 A x 2.5 V power rail
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • User LED
  • Evenly-spread supply pins for good signal integrity

Assembly options for cost or performance optimization available upon request.

 

Signals, Interfaces and Pins

System Controller I/O Pins

Special purpose pins used by TE0729

NameNote
NRST 
NRST_IN 

Boot Modes

TE0729 supports primary boot from

  • JTAG
  • SPI Flash
  • SD Card

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

The boot modes are controlled by the Pins 'BOOT1' and 'BOOT2' on the board to board (B2B) connector.

BOOTMODE1

BOOTMODE2Boot mode
LOWLOW 
LOWHIGH 
HIGHLOW 
HIGHHIGH 

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J2.

SignalB2B Pin
TCKJ2:  119
TDIJ2:  115
TDOJ2:  117
TMSJ2:  113

JTAGSEL pin in J2 should be kept low or grounded for normal operation.

 

Clocking

ClockFrequencyICFPGANotes
PS CLK33.3333 MHzU14PS_CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHY reference25 MHzU10- 
USB PHY reference52 MHzU12- 

 

Processing System (PS) Peripherals

PeripheralICDesignatorPSMIONotes
EEPROM I2C24AA025E48T-I/OTU8I2C0MIO10, MIO11MAC Address
EEPROM I2C24AA025E48T-I/OTU9I2C0MIO10, MIO11MAC Address
EEPROM I2C24AA025E48T-I/OTU20I2C0MIO10, MIO11MAC Address
RTCISL12020MIRZU22I2C0MIO10, MIO11Temperature compensated real time clock
RTC InterruptISL12020MIRZU22GPIOMIO46Real Time Clock Interrupt
SPI FlashS25FL256SAGBHI20U13QSPI0MIO1..MIO6 
Ethernet0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U3ETH0MIO16...MIO27 
Ethernet0 10/100/1000 Mbps PHY Reset  GPIOMIO51 
Ethernet1 10/100 Mbps PHYKSZ8081MLXCAU17-(EMIO) 
Ethernet1 10/100 Mbps PHY Reset  -(EMIO) 
Ethernet2 10/100 Mbps PHYKSZ8081MLXCAU19-(EMIO) 
Ethernet2 10/100 Mbps PHY Reset  -(EMIO) 
USBUSB3320C-EZKU11USB0MIO28...MIO39 
USB Reset  GPIOMIO49 
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U5SDIO0MIO40...MIO45depending on state of pin MIO48 'SEL_SD'

 

Default MIO mapping:

MIOConfigured asB2BNotes
 0GPIO J2-87 B2B
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7GPIO -Red LED D8
8 - - -
9GPIOJ2-88B2B
10I2C0 SDAJ2-90B2B 
11I2C0 SCLJ2-92B2B
12I2C1 SDAJ2-93 B2B (SDA on-board I2C, also configurable as GPIO by user)
13I2C1 SCLJ2-95 B2B (SCL on-board I2C, also configurable as GPIO by user)
14USART0 RXJ2-94B2B (RX on-board UART, also configurable as GPIO by user)
15USART0 TXJ2-96B2B (TX on-board UART, also configurable as GPIO by user)
16..27ETH0 RGMII
28..39USB0 ULPI
40SDIO0J2-100 B2B depending on state of pin MIO48 'SEL_SD'
41SDIO0J2-102 B2B depending on state of pin MIO48 'SEL_SD'
42SDIO0J2-104 B2B depending on state of pin MIO48 'SEL_SD'
43SDIO0J2-106 B2B depending on state of pin MIO48 'SEL_SD'
44SDIO0J2-108 B2B depending on state of pin MIO48 'SEL_SD'
45SDIO0J2-110 B2B depending on state of pin MIO48 'SEL_SD'
46GPIO-RTC Interrupt
47
48 GPIOSEL_SDselect source between e-MMC / baseboard SD-Card 
49GPIO -USB Reset
50GPIO -ETH0 Interrupt
51GPIO -ETH0 Reset
52ETH0 -MDC

53

ETH0 -MDIO

 

 

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