Overview
The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020).
This SoM has following peripherals on board:
- 1 x Gbps Ethernet PHY transceiver
- 2 x 100 Mbps Ethernet PHY transceivers
- 512 MByte DDR3 Memory
- 32 MByte SPI Flash Memory
- eMMC (4 GByte in standard configuration)
- USB PHY transceiver
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
Key Features
- Industrial-grade Xilinx Zynq-7000 (XC7Z020) SoM
- Rugged for shock and high vibration
- 2 x ARM Cortex-A9
- 1 x 10/100/1000 Mbps Ethernet transceiver PHY
- 2 x 10/100 Mbps Ethernet transceiver PHYs
- 3 x MAC-Address EEPROMs
- 16-Bit wide 512 MByte DDR3 SDRAM
- 32 MByte QSPI-Flash-Memory
- 4 GByte e-NAND-Flash-Memory (embedded eMMC Memory)
- USB 2.0 high-speed ULPI transceiver
- Plug-on module with 2 x 120-pin high-speed hermaphroditic strips
- 136 FPGA I/Os (58 LVDS pairs possible) and 6 PS MIOs available on board-to-board connectors
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- 1.5 A x 2.5 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
Signals, Interfaces and Pins
System Controller I/O Pins
Special purpose pins used by TE0729
| Name | Note |
|---|---|
| NRST | |
| NRST_IN |
Boot Modes
TE0729 supports primary boot from
- JTAG
- SPI Flash
- SD Card
Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).
The boot modes are controlled by the Pins 'BOOT1' and 'BOOT2' on the board to board (B2B) connector.
BOOTMODE1 | BOOTMODE2 | Boot mode |
|---|---|---|
| LOW | LOW | |
| LOW | HIGH | |
| HIGH | LOW | |
| HIGH | HIGH |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided by connector J2.
| Signal | B2B Pin |
|---|---|
| TCK | J2: 119 |
| TDI | J2: 115 |
| TDO | J2: 117 |
| TMS | J2: 113 |
JTAGSEL pin in J2 should be kept low or grounded for normal operation.
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
| 10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
| USB PHY reference | 52 MHz | U12 | - |
Processing System (PS) Peripherals
| Peripheral | IC | Designator | PS | MIO | Notes |
|---|---|---|---|---|---|
| EEPROM I2C | 24AA025E48T-I/OT | U8 | I2C0 | MIO10, MIO11 | MAC Address |
| EEPROM I2C | 24AA025E48T-I/OT | U9 | I2C0 | MIO10, MIO11 | MAC Address |
| EEPROM I2C | 24AA025E48T-I/OT | U20 | I2C0 | MIO10, MIO11 | MAC Address |
| RTC | ISL12020MIRZ | U22 | I2C0 | MIO10, MIO11 | Temperature compensated real time clock |
| RTC Interrupt | ISL12020MIRZ | U22 | GPIO | MIO46 | Real Time Clock Interrupt |
| SPI Flash | S25FL256SAGBHI20 | U13 | QSPI0 | MIO1..MIO6 | |
| Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U3 | ETH0 | MIO16...MIO27 | |
| Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO51 | |||
| Ethernet1 10/100 Mbps PHY | KSZ8081MLXCA | U17 | - | (EMIO) | |
| Ethernet1 10/100 Mbps PHY Reset | - | (EMIO) | |||
| Ethernet2 10/100 Mbps PHY | KSZ8081MLXCA | U19 | - | (EMIO) | |
| Ethernet2 10/100 Mbps PHY Reset | - | (EMIO) | |||
| USB | USB3320C-EZK | U11 | USB0 | MIO28...MIO39 | |
| USB Reset | GPIO | MIO49 | |||
| e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U5 | SDIO0 | MIO40...MIO45 | depending on state of pin MIO48 'SEL_SD' |
Default MIO mapping:
| MIO | Configured as | B2B | Notes |
|---|---|---|---|
| 0 | GPIO | J2-87 | B2B |
| 1 | QSPI0 | - | SPI Flash-CS |
| 2 | QSPI0 | - | SPI Flash-DQ0 |
| 3 | QSPI0 | - | SPI Flash-DQ1 |
| 4 | QSPI0 | - | SPI Flash-DQ2 |
| 5 | QSPI0 | - | SPI Flash-DQ3 |
| 6 | QSPI0 | - | SPI Flash-SCK |
| 7 | GPIO | - | Red LED D8 |
| 8 | - | - | - |
| 9 | GPIO | J2-88 | B2B |
| 10 | I2C0 SDA | J2-90 | B2B |
| 11 | I2C0 SCL | J2-92 | B2B |
| 12 | I2C1 SDA | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) |
| 13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) |
| 14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) |
| 15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) |
| 16..27 | ETH0 | RGMII | |
| 28..39 | USB0 | ULPI | |
| 40 | SDIO0 | J2-100 | B2B depending on state of pin MIO48 'SEL_SD' |
| 41 | SDIO0 | J2-102 | B2B depending on state of pin MIO48 'SEL_SD' |
| 42 | SDIO0 | J2-104 | B2B depending on state of pin MIO48 'SEL_SD' |
| 43 | SDIO0 | J2-106 | B2B depending on state of pin MIO48 'SEL_SD' |
| 44 | SDIO0 | J2-108 | B2B depending on state of pin MIO48 'SEL_SD' |
| 45 | SDIO0 | J2-110 | B2B depending on state of pin MIO48 'SEL_SD' |
| 46 | GPIO | - | RTC Interrupt |
| 47 | - | - | - |
| 48 | GPIO | SEL_SD | select source between e-MMC / baseboard SD-Card |
| 49 | GPIO | - | USB Reset |
| 50 | GPIO | - | ETH0 Interrupt |
| 51 | GPIO | - | ETH0 Reset |
| 52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
I2C Interface
The on-board I2C components are connected to MIO10 and MIO11 and configured as I2C0 by default.
I2C addresses for on-board components:
| Device | I2C-Address | Notes |
|---|---|---|
| EEPROM for MAC1 | 0x50 | |
| EEPROM for MAC2 | 0x81 | |
| EEPROM for MAC3 | 0x82 | |
| RTC | ||
| Battery backed RAM | integrated in RTC |
B2B I/O
Number of I/O's connected to the SoC's I/O bank and B2B connector:
| Bank | Type | Jx | IO count | IO Voltage | Notes |
|---|---|---|---|---|---|
| 500 | MIO | J2-87 J2-88 | 2 | 3,3 V | MIO0, MIO9 |
| 500 | MIO | J2-93 J2-95 J2-94 J2-96 | 4 | 3,3 V | configured as I2C1 and USART0 by default, configurable as GPIO by user |
| 13 | HR | J1 | 48 | user | |
| 33 | HR | J1 | 48 | user | |
| 35 | HR | J2 | 30 | 3,3 V | |
| 34 | GPIO | J2 | 10 | 2,5 V | configured as DISP_RX by default, configurable as GPIO by user |
For detailed information about the pin out, please refer to the Master Pinout Table.
Peripherals
LED's
There are 3 LED's on TE0729:
| LED | Color | Connected to | Notes |
|---|---|---|---|
| D1 | red | System Controller | Global Status LED |
| D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
| D8 | red | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured.
This LED will not operate if the System Controller can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module.
Ethernet
The TE0729 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U3). The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector J2.
The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U10).
PHY connection:
| PHY PIN | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | - | pin J2-57 in B2B connector |
| LED1 | - | - | pin J2-59 in B2B connector |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | Pin connected to GND, PHY Address is strapped to 0x00 by default |
| RESETn | MIO51 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B J2 connector |
| MDI | - | - | on B2B J2 connector |
USB
The USB PHY USB3320 from Microchip is used on the TE0729. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U12).
PHY connection:
| PHY Pin | Zynq Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
| REFCLK | - | - | 52MHz from on board oscillator (U12) |
| REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
| RESETB | MIO49 | - | Active low reset |
| CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
| DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U22). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address ???.
General purpose RAM is accessed at I2C slave address ???.
This RTC IC is supported in Linux so it can be used as hwclock device.
MAC-Address EEPROMs
Three Microchip 24AA025E48 EEPROMs (U8, U9, U20) are used on the TE0729. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50 for MAC-Address1 (U8), 0x81 for MAC-Address1 (U9), 0x82 for MAC-Address1 (U20).
Power
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Power Supplies
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank Voltages
| Bank | Voltage | max. Value | note |
|---|---|---|---|
| 501 | 1,8 V | - | ETH0 / USB0 / SDIO0 |
| 500 | 3,3 V | - | SPI / I2C / UART |
| 502 | 1,5 V | - | DDR3-RAM |
| 13 | user | 3,3 V | connected to 3,3V by default by 0 Ohm Resistor R36 |
| 33 | user | 3,3 V | connected to 3,3V by default by 0 Ohm Resistor R55 |
| 34 | 2,5 V | - | ETH / DISP |
| 35 | 3,3 V | - | GPIO |
Initial Delivery state
| Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROMs | User content not programmed | Valid MAC Address from manufacturer |
| e-MMC memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed | |
Hardware Revision History
| Revision | Changes |
|---|---|
01 | Prototypes |
| 02 | Prototypes |
| 03 | First production release |
Technical Specification
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | V | |
| VBat supply voltage | -1 | 6.0 | V | |
| PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0729 does not have HP banks |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal |
Storage Temperature | -40 | +85 | C | |
| Storage Temperature without the ISL12020MIRZ | -55 | +100 | C |
Assembly variants for higher storage temperature range on request
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).
Overview
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