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Table of Contents

Overview

The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Contact us for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

 

This SoM has following peripherals on board:

  • 2 x Gbps Ethernet PHY transceiver
  • 2 x 512 MByte DDR3 SDRAM
  • 32 MByte QSPI Flash Memory for configuration, operation and to store data
  • eMMC (4 GByte in standard configuration)
  • 2 x USB PHY transceiver
  • 16 GTX high-performance transceiver lanes
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

Key Features

  • Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
  • Rugged for shock and high vibration
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte DDR3 SDRAM (2 x 16-Bit wide 512 MByte DDR3 SDRAM)
    • 32 MByte QSPI Flash memory
    • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
    • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64GByte)
  • 2 x MAC-Address EEPROMs
  • optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)
  • optional 2 x 32 MByte HyperFLASH
  • Temperature compensated RTC (real-time clock)
  • Si5338 PLL for GTX Transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver lanes
    • GT transceiver clock inputs
    • 254 FPGA I/O's (125 LVDS pairs)
  • On-board high-efficiency DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

Assembly options for cost or performance optimization available upon request.

Signals, Interfaces and Pins

System Controller I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782

NameNote
BOOTMODE 
CONFIGX 
JTAGENB 
RESIN 
CLPD_GPIO0user GPIO
CLPD_GPIO1user GPIO
CLPD_GPIO2user GPIO
CLPD_GPIO3user GPIO
CLPD_GPIO4user GPIO
CLPD_GPIO5user GPIO

Boot Modes

TE0782 supports primary boot from

  • SPI Flash

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
TCKJ3:  141
TDIJ3:  147
TDOJ3:  148
TMSJ3:  1142

 

CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

SignalB2B Pin
M_TCKJ3:  81
M_TDIJ3:  87
M_TDOJ3:  82
M_TMSJ3:  88

JTAGENB pin in J2 should be kept low or grounded for normal operation.

Clocking

ClockFrequencyICFPGANotes
PS CLK33.3333 MHzU61PS_CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHYs reference25 MHzU11- 
USB PHY reference52 MHzU7- 

PLL reference

25 MHz

U3

-

 

GT REFCLK1

-

B2B

AC7/AC8

Externally supplied from base

GT REFCLK4

-

B2B

U7/U8

Externally supplied from base

quad programmable clock (I2C)

SI5338A

userU2-

GT REFCLK0

GT REFCLK3

GT REFCLK5

GT REFCLK6

Processing System (PS) Peripherals

PeripheralICDesignatorPSMIONotes
QSPI FlashS25FL256SAGBHI20U38QSPI0MIO1...MIO6 
Ethernet0 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U18ETH0; GPIO BANK35MIO16...MIO27, MIO52, MIO53 
Ethernet0 10/100/1000 Mbps PHY Reset  GPIOMIO7ETH1_RESET33 -> CPLD -> ETH1_RESET
Ethernet1 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U20GPIO BANK9, BANK35- 
Ethernet1 10/100/1000 Mbps PHY Reset  GPIO BANK35, Pin B15- 
USB0USB3320C-EZKU4USB0MIO28...MIO39 
USB0 Reset  GPIOMIO0OTG_RESET33 -> CPLD -> OTG_RESET
USB1USB3320C-EZKU8USB1MIO40...MIO51 
USB1 Reset  GPIOMIO0OTG_RESET33 -> CPLD -> OTG_RESET
 e-MMC (embedded e-MMC)MTFC4GMVEA-4M IT  U15SDIO0MIO10...MIO15 
EEPROM I2C24LC128-I/STU26GPIO BANK35, Pin L14/L15-??
EEPROM I2C24AA025E48T-I/OTU22GPIO BANK35, Pin L14/L15-MAC Address
EEPROM I2C24AA025E48T-I/OTU24GPIO BANK35, Pin L14/L15-MAC Address
RTCISL12020MIRZU17GPIO BANK35, Pin L14/L15-Temperature compensated real time clock
RTC InterruptISL12020MIRZU17--RTC_INT -> CPLD

Default MIO mapping

MIOConfigured asB2BNotes
0OTG-RST33 -connected to CPLD
1QSPI0 -SPI Flash-CS
2QSPI0 -SPI Flash-DQ0
3QSPI0 -SPI Flash-DQ1
4QSPI0 -SPI Flash-DQ2
5QSPI0 -SPI Flash-DQ3
6QSPI0 -SPI Flash-SCK
7ETH1_RESET33 -connected to CPLD
8GPIO-connected to CPLD and Pull-Up 3.3V
9GPIO-connected to CPLD
10MMC-D0--
11MMC-CMD--
12MMC-CCLK--
13MMC-D1--
14MMC-D2--
15MMC-D3--
16..27ETH0-Ethernet RGMII PHY
28..39USB0-USB0 ULPI PHY
40...51USB1-USB1 ULPI PHY
52ETH0 MDC--
53ETH0 MDIO--

I2C Interface

The on-board I2C components are connected to BANK35, Pin L15 (I2C_SDA) and to BANK35, Pin L14 (I2C_SCL).

I2C addresses for on-board components

DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53-
EEPROM24AA025E48T-I/OTU220x50MAC Address
EEPROM24AA025E48T-I/OTU240x51MAC Address
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57integrated in RTC
CLOCK GENERATORSI5338A-B-GMRU20x70Quad reference clock for GTX transceiver lanes
CPLDLCMXO2-1200HC-4TG100IU14user-

B2B I/O

Number of I/O's connected to the SoC's I/O bank and B2B connector

BankTypeB2BIO countIO VoltageNotes
10HRJ344user22 LVDS-pairs possible
11HRJ340user20 LVDS-pairs possible
12HRJ240user20 LVDS-pairs possible
13HRJ240user20 LVDS-pairs possible
33HRJ148user23 LVDS-pairs possible
34HRJ242user20 LVDS-pairs possible

For detailed information about the pin out, please refer to the Master Pinout Table.

Peripherals

LED's

 There are 3 LED's on TE0729:

LEDColorConnected toNotes
D1redSystem ControllerGlobal Status LED
D2greenDONEInverted DONE, ON when FPGA not configured
D8redMIO7OFF when PS7 not booted and not controlling MIO7 by software, else user controlled

LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured.

This LED will not operate if the System Controller can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module.

Ethernet

The TE0729 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U3) and has in this TRM the identifier Ethernet0. The Ethernet0 PHY RGMII Interface is connected to the Zynq ETH0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.

SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector J2.

The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U10).

Ethernet0 PHY connection:

PHY PINZYNQ PSZYNQ PLNotes
MDC/MDIOMIO52, MIO53--
LED0--pin J2-57 on B2B connector
LED1--pin J2-59 on B2B connector
LED2/InterruptMIO46--
CONFIG--Pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnMIO51--
RGMIIMIO16..MIO27--
SGMII--on B2B J2 connector
MDI--on B2B J2 connector

 

The TE0729 SoM is also equipped with two additional Microchip KSZ8081MLXCA Ethernet-PHYs (ICs U17 and U19) to provide further 10/100 Mbps Ethernet interfaces with the identifiers Ethernet1 and Ethernet2. Those PHYs can be operated as Ethernet interfaces 10Base-T or 100Base-T with for 4-wires twisted pair cable. The reference clock input of both PHYs is supplied from the same 25MHz oscillator (U10), which also provides Ethernet0 Gigabit PHY with a reference clock signal.

Ethernet1 PHY connection to B2B-connectors:

PHY PINB2Bnotes
ETH1_RX_PJ2-26-
ETH1_RX_NJ2-28-
ETH1_TX_PJ2-20-
ETH1_TX_NJ2-22-
ETH1_LED0J2-34Status LED
ETH1_LED1J2-32Transmission LED

Ethernet2 PHY connection to B2B-connectors:

PHY PINB2Bnotes
ETH2_RX_PJ2-2-
ETH2_RX_NJ2-4-
ETH2_TX_PJ2-8-
ETH2_TX_NJ2-10-
ETH2_LED0J2-16Status LED
ETH2_LED1J2-14Transmission LED

All other pins of the PHYs are connected to Bank34 of Zynq, see schematic for further details.

USB

The USB PHY USB3320 from Microchip is used on the TE0729. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.

The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U12).  

PHY connection:

PHY PinZynq PinB2B NameNotes
ULPIMIO28..39-Zynq USB0 MIO pins are connected to the PHY
REFCLK--52MHz from on board oscillator (U12)
REFSEL[0..2]--000 GND, select 52MHz reference Clock
RESETBMIO49-Active low reset
CLKOUTMIO36-Connected to 1.8V selects reference clock operation mode
DP,DM-OTG_D_P, OTG_D_NUSB Data lines
CPEN-VBUS_V_ENExternal USB power switch active high enable signal
VBUS-USB_VBUSConnect to USB VBUS via a series resistor. Check reference schematic
ID-OTG_IDFor an A-Device connect to ground, for a B-Device left floating

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

RTC

An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U22). Battery voltage must be supplied to the module from the main board.

Battery backed registers are accessed at I2C slave address 0x57.

General purpose RAM is accessed at I2C slave address 0x6F.

This RTC IC is supported in Linux so it can be used as hwclock device.

MAC-Address EEPROMs

Three Microchip 24AA025E48 EEPROMs (U8, U9, U20) are used on the TE0729. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50 for MAC-Address1 (U8), 0x81 for MAC-Address2 (U9)0x82 for MAC-Address3 (U20).

Power

For startup, a power supply with minimum current capability of 3A is recommended.

VIN and 3.3VIN can be connected to the same source (3.3 V).

Power Supplies

Supply Voltage

Voltage Range

note

Vin

3.3 V to 5.5 V

Typical 200 mA, depending on customer design and connections

Vin 3.3V3.3 V

Typical 50 mA, depending on customer design and connections

Bank Voltages

BankVoltagemax. Valuenote
5011,8 V-ETH0 / USB0 / SDIO0
5003,3 V-SPI / I2C / UART
5021,5 V-DDR3-RAM
13user3,3 Vconnected to 3,3V by default by 0-Ohm-Resistor R36
33user3,3 Vconnected to 3,3V by default by 0-Ohm-Resistor R55
342,5 V-ETH / DISP
353,3 V-GPIO

Initial Delivery state

Storage device nameContentNotes

24AA025E48 EEPROMs

User content not programmed

Valid MAC Address from manufacturer
e-MMC Flash-MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

 

SPI Flash main array

demo design

 

EFUSE USER

Not programmed

 

EFUSE Security

Not programmed

 

Hardware Revision History

RevisionChanges

01

Prototypes

02First production release

Technical Specification

Absolute Maximum Ratings

ParameterMinMaxUnitsNotes

Vin supply voltage

-0.3

6.0

V

 

Vin33 supply voltage

-0.4

3.6

V

 
VBat supply voltage-16.0V 
PL IO Bank supply voltage for HR I/O banks (VCCO)-0.53.6V 
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55VTE0729 does not have HP banks

Voltage on Module JTAG pins

-0.4

VCCO_0+0.55

V

VCCO_0 is 3.3V nominal

Storage Temperature

-40

+85

C

 
Storage Temperature without the ISL12020MIRZ-55+100C 
Assembly variants for higher storage temperature range on request
Please check Xilinx Datasheet for complete list of Absolute maximum and recommended operating ratings for the Zynq device (DS181 Artix or DS182 Kintex).

Recommended Operating Conditions

ParameterMinMaxUnitsNotesReference document
Vin supply voltage2.55.5V  
Vin33 supply voltage3.1353.465V  
VBat supply voltage2.75.5V  
PL IO Bank supply voltage for HR I/O banks (VCCO)1.143.465V Xilinx document DS191
I/O input voltage for HR I/O banks(*)(*)V(*) Check datasheetXilinx document DS191 and DS187
Voltage on Module JTAG pins3.1353.465VVCCO_0 is 3.3 V nominal 

Physical Dimensions

  • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

All dimensions are shown in mm.

Temperature Ranges

Commercial grade modules

All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Industrial grade modules

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Weigt

Part

g

Plain module

gSet of bolts and nuts

Document Change History

daterevisionauthorsdescription
2006-06-14v10initial release

Disclaimer

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