SREC Loader with U-Boot
This one of easiest solutions to implement full multiboot application for any Xilinx 7 Series or Ultrascale FPGA.
A Microblaze based system should be made with following IP Core from Xilinx free Vivado IP Catalog:
- AXI_QSPI
- AXI_HWICAP
- AXI_UARTLITE
- AXI_GPIO
- MIG (for External Memory access)
| Offset | Size | Content | Notes |
|---|---|---|---|
| Application bitstream #2 | |||
| Application bitstream #2 | |||
| u-boot converted to SREC format | |||
| 0x2000 | u-boot flash environment | ||
| 0x000000 | GOLDEN bitstream with SREC Loader |
Xilinx SREC SPI loader is used to bootstrap u-boot into external memory, then u-boot is used for all flash operations as required. The image to be written can be loaded to external RAM and then written to SPI Flash as needed.
Step by Step
- FPGA loads from address 0, Microblaze starts
Overview
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