TE0782-TRM

Overview

The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

This SoM has following peripherals on board:

• 2 x Gbps Ethernet PHY transceiver
• 16-Bit wide 2 x 512 MByte DDR3 SDRAM
• 32 MByte QSPI Flash Memory for configuration, operation and to store data
• eMMC (4 GByte in standard configuration)
• 2 x USB PHY transceiver
• 16 GTX high-performance transceiver lanes
• powerful switch-mode power supplies for all on-board voltages
• large number of configurable I/Os is provided via rugged high-speed stacking strips

Block Diagramm

Key Features

• Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
• Rugged for shock and high vibration
• Dual ARM Cortex-A9 MPCore
  • 1 GByte DDR3 SDRAM (2 x 16-Bit wide 512 MByte DDR3 SDRAM)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64GByte)
• 2 x MAC-Address EEPROMs
• optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM) or optional 2 x 64 MByte HyperFLASH
• Temperature compensated RTC (real-time clock)
• Si5338 PLL for GTX Transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver lanes
  • GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

Assembly options for cost or performance optimization available upon request.

Signals, Interfaces and Pins

System Controller CPLD I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782

Small CPLD controls some functions of the SoM, this CPLD can be updated by the end user if support is designed on customer base.

Boot Modes

TE0782 supports primary boot from

• SPI Flash

Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

CPLD-JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.

Clocking

Silabs Multisynth PLL Si5338 can deliver GT reference clocks to all 4 GT Banks. Additionally a GT Reference clock can be generated on the base board for any of the 4 GT Banks. There is reference clock available on the TE0782 for Si5338, there is no need to supply a master reference clock from the base.

Processing System (PS) Peripherals

Default MIO mapping

Pin Definitions

Pins named _vrn and _vrp are connected to ZYNQ PL HP Bank special purpose pins VRN/VRP. If needed they can be connected to DCI calibration resistors on the base. If not, then those pins can be used as general purpose I/O.

Bank B35 has 100 ohm DCI calibration resistors installed on TE0782, it is also possible to "borrow" the DCI calibration from B35 for banks B34, and B33. For detailed usage of the DCI check Xilinx documentation.

I2C Interface

The on-board I2C components are connected to BANK35, Pin L15 (I2C_SDA) and to BANK35, Pin L14 (I2C_SCL).

I2C addresses for on-board components

B2B I/O

Number of I/O's connected to the SoC's I/O bank and B2B connector

For detailed information about the pin out, please refer to the Master Pinout Table.

Peripherals

LED's

D1 - Onboard RED LED

This function depend on the CPLD revision.

D2 - Onboard GREEN LED

Green LED connected to MIO8

Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).

ETH1 PHY connection:

ETH2 PHY connection:

USB

The TE0782 is equipped with two USB PHYs USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHYs is supplied from an on board 52MHz oscillator (U7).  

USB0 PHY connection:

USB1 PHY connection:

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

RTC

An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U17). Battery voltage must be supplied to the module from the main board.

Battery backed registers are accessed at I2C slave address 0x57.

General purpose RAM is accessed at I2C slave address 0x6F.

This RTC IC is supported in Linux so it can be used as hwclock device.

PLL

The TE0782 is also equipped with a Silicon Labs I2C-programmable clock generator Si5338A (U2). The Si5338 can be programmed using the I2C-bus, to change the frequency on its outputs. It is accessible on the I2C slave address 0x70.

PLL connection:

MAC-Address EEPROMs

Two Microchip 24AA025E48 EEPROMs (U22 and U24) are used on the TE0782. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. Those are accessible by the I2C slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Power

Input Power Supply

Bank Voltages

Initial Delivery state

Hardware Revision History

Technical Specification

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Please download the assembly diagram for exact values.

• Module size: 85 mm × 85 mm.

• Mating height with standard connectors: 5 mm

• PCB thickness: 1,7 mm

All dimensions are shown in mm.

Temperature Ranges

Commercial grade modules

All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Industrial grade modules

All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Document Change History

date	revision	authors	description
2016-06-27	v10		initial release

Disclaimer

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