Basic project to generate SDSoC Platform project and petalinux. Various SDSoC examples are included.
Refer to http://trenz.org/te0xyz-info for the current online version of this manual and other available documentation.
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2018-11-06 | 2018.2 | TE0720-TE0720_zsys_SDSoC-vivado_2018.2-build_03_20181106093337.zip | Zdenek Pohl, Jiri Kadlec | initial release |
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Software | Version | Note |
---|---|---|
SDx(SDSoC) | 2018.2 | needed |
PetaLinux | 2018.2 | needed |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
te0720-03-2if | 2if | REV02, REV03 | 1GB | 32 | ||
te0720-03-2ifc3 | 2if | REV02, REV03 | 1GB | 32 | 2.5 mm connector | |
te0720-03-2ifc8 | 2if | REV02, REV03 | 1GB | 32 | 32GB eMMC | |
te0720-03-1qf | 1qf | REV02, REV03 | 1GB | 32 | ||
te0720-03-1qfa | 1qf | REV03 | 1GB | 32 | Micron instead of Spansion Flash | |
te0720-03-1cf | 1cf | REV02, REV03 | 1GB | 32 | ||
te0720-03-1cfa | 1cf | REV02, REV03 | 1GB | 32 | 8GB eMMC | |
te0720-03-2ef | 2ef | REV02, REV03 | 1GB | 32 | ||
te0720-03-14s-1c | 14s | REV02, REV03 | 1GB (L) | 32 | ||
te0720-03-2ifa | 2if | REV03 | 1GB | 32 | Micron instead of Spansion Flash |
Design supports following carriers:
Carrier Model | Notes |
---|---|
--- |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
For general structure and of the reference design, see Project Delivery - AMD devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
SDSoC | <design name>/../SDSoC_PFM | SDSoC Platform will be generated by TE Scripts or as separate download |
Type | Location | Notes |
---|---|---|
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Basic Reference Design and SDSoC Platform projects for Win OS are available on:
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
This cheaper describes how you can create SDSoC platform project from special Trenz Electronik Vivado projects.
This chapter is optional: Prebuilt SDSoC platform projects for Win OS are also available on the download area.
Source location: \sw_lib\sw_apps
TE modified 2018.2 FSBL
Changes:
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
Changes:
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
/include/ "system-conf.dtsi" / { };
Example | Comment |
---|---|
Array partition | This example shows how to use array partitioning to improve performance of a hardware function |
Burst rw | This is simple example of using AXI4-master interface for burst read and write |
Custom data type | This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR |
Data access random | This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern |
Dependence inter | This is a simple example to demonstrate inter dependence attribute. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance. |
Direct connect | This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency |
Dma sg | This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator |
Dma simple | This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator |
File IO Dense Optical Flow | Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input. |
File IO Stereo Block Matching | Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv as input. |
File IO Video Processing | Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames. |
Full array 2d | This is a simple example of accessing full data from 2D array |
Hello vadd | This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function |
Lmem 2rw | This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory |
Loop fusion | This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function. |
Loop perfect | This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop. |
Loop pipeline | This example demonstrates how loop pipelining can be used to improve the performance of a hardware function. |
Loop reorder | This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering. |
Row array 2D | This is a simple example of accessing each row of data from 2D array |
Shift register | This example demonstrates how to shift values in each clock cycle |
Sys port | This is a simple example which demonstrates sys_port usage |
Systolic array | Matrix multiplication implemented as systolic array |
Wide memory rw | Wide memory read write 128 bit wide |
Window array 2d | This is a simple example of accessing window of data from 2D array |
To get content of older revision got to "Change History" of this page and select older document revision number.
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