Nios V/m design example with SDRAM controller (AXI4), flash memory, 3-axis Accelerometer and different LED sequences.
Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.
Date | Quartus | Project Built | Authors | Description |
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2024-02-07 | 22.1 Lite | TEI0001-test_board_noprebuilt-quartus_22.1std.2-20240207162519.zip | Thomas Dück |
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2022-04-21 | 21.1 Lite | TEI0001-test_board_noprebuilt-quartus_21.1.0-20220421150137.zip TEI0001-test_board-quartus_21.1.0-20220421150228.zip | Thomas Dück |
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2021-07-09 | 20.1 Lite | TEI0001-test_board_noprebuilt-quartus_20.1.1-20210709113727.zip TEI0001-test_board-quartus_20.1.1-20210709113644.zip | Thomas Dück |
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2020-10-19 | 19.1 Lite | TEI0001-test_board_noprebuilt-quartus_19.1.0-20201019101714.zip TEI0001-test_board-quartus_19.1.0-20201019101651.zip | Thomas Dück |
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2020-07-07 | 19.1 Lite | TEI0001-test_board_noprebuilt-quartus_19.1.0-20200707153033.zip TEI0001-test_board-quartus_19.1.0-20200707153205.zip | Thomas Dück |
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2020-05-12 | 19.1 Lite | TEI0001-test_board_noprebuilt-quartus_19.1.0-20200512095852.zip TEI0001-test_board-quartus_19.1.0-20200512100037.zip | Thomas Dück |
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2019-11-11 | 18.1 | TEI0001-test_board_noprebuilt-quartus_18.1-20191111104201.zip TEI0001-test_board-quartus_18.1-20191111104348.zip | Thomas Dück |
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2019-10-28 | 18.1 | TEI0001-test_board_noprebuilt-quartus_18.1-20191028120819.zip TEI0001-test_board-quartus_18.1-20191028120521.zip | Thomas Dück |
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2019-04-02 | 18.1 | TEI0001-03-08-C8-test_board-quartus_18.1-20190402.zip | Thomas Dück |
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Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Software | Version | Note |
---|---|---|
Quartus Prime Lite | 22.1std | Nios V license is needed. For more information see: Intel Nios V Processors |
RiscFree IDE for Intel FPGAs | 22.1std | needed |
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | Flash memory | Others | Notes |
---|---|---|---|---|---|---|
TEI0001-02-08-C8* | DBC83 | REV02 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-02-16-C8 | FBC83 | REV02 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-03-08-C8 | DBC83 | REV03 | 8MByte | 8Mbyte | -- | -- |
TEI0001-03-16-C8 | FBC83 | REV03 | 8MByte | 8Mbyte | -- | -- |
TEI0001-03-16-C8A | FBC84 | REV03 | 32MByte | 8Mbyte | -- | -- |
TEI0001-03-DBC83A | DBC83 | REV03 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-03-FBC83A | FBC83 | REV03 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-03-FBC84A | FBC84 | REV03 | 32MByte | 8Mbyte | -- | -- |
TEI0001-04-DBC83A | DBC83 | REV04 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-04-FBC83A | FBC83 | REV04 | 8Mbyte | 8Mbyte | -- | -- |
TEI0001-04-FBC84A | FBC84 | REV04 | 32MByte | 8Mbyte | -- | -- |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
--- |
*used as reference
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
Micro USB cable for JTAG/UART | -- |
*used as reference
For general structure and of the reference design, see Project Delivery - Intel devices
Type | Location | Notes |
---|---|---|
Quartus | <project folder>/source_files/quartus | Quartus project will be generated by TE Scripts |
Software | <project folder>/source_files/software | Additional software will be generated by TE Scripts |
File | File-Extension | Description |
---|---|---|
SOPC Information File | *.sopcinfo | File with description of the *.qsys file to create software for the target hardware |
Programmer Object File | *.pof | FPGA configuration file |
Diverse Reports | --- | Report files in different formats |
Software Application File | *.elf | Software application for NIOS II processor system |
BIN-File | *.bin | Image of the software application for flash memory |
Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.
TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
select COM Port
Win OS: see device manager
Linux OS: see dmesg | grep tty (UART is *USB1)
The block designs may differ depending on the assembly variant.
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
Software example to test TEI0001 module.
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
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2022-06-15 | v.16 | Thomas Dück |
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2021-07-09 | v.14 | Thomas Dück |
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2020-10-09 | v.12 | Thomas Dück |
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2020-05-13 | v.10 | Thomas Dück |
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2019-11-11 | v.8 | Thomas Dück |
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2019-10-29 | v.6 | Thomas Dück |
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2019-04-03 | v.4 | Thomas Dück |
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-- | all | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | -- |
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