disclaimer

Because of incompatibility reasons with some customer carriers the current CPLD Firmware revision REV02 and REV02.1 are only for testing purposes and we recommend to use the old REV01.
For cpld firmware REV01 - download and documentation please follow:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/8.5x8.5/TE0782/REV02/Firmware/archive


Overview


Firmware for PCB CPLD with designator U14. CPLD Device in Chain: LCMX02-1200HC

Feature Summary

  • Power Management

  • Reset Management
  • Boot Mode

  • LED

  • I2C
  • UART

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank VoltageDescription
BM0/MIO5out47NoneLVCMOS33Boot Mode Pin
BM2/MIO4out48NoneLVCMOS33Boot Mode Pin
BM3/MIO2out49NoneLVCMOS33Boot Mode Pin
BOOTMODEin99UPLVCMOS33Boot Mode Pin from B2B / Used for UART as input to MIO9
CONFIGXout98UPLVCMOS33MIO8 to B2B / Used for UART as output from MIO8
CPLD_GPIO0
12--/ currently_not_used
CPLD_GPIO1
11--/ currently_not_used
CPLD_GPIO2
10--/ currently_not_used
CPLD_GPIO3
9--/ currently_not_used
CPLD_GPIO4
8--/ currently_not_used
CPLD_GPIO5
7--/ currently_not_used
CPLD_IO
54--/ currently_not_used
DONEin34UPLVCMOS33FPGA Done Pin
EN_1.0V_MGT / EN_1V0_MGTout20NoneLVCMOS33Power control
EN_1.2V_MGT / EN_1V2_MGTout18NoneLVCMOS33Power control
EN_1.8Vout16NoneLVCMOS33Power control
EN_1Vout21NoneLVCMOS33Power control
EN_3.3Vout15NoneLVCMOS33Power control
ETH1_RESETout53NoneLVCMOS18ETH Reset
ETH1_RESET33in43UPLVCMOS33ETH Reset from MIO7
I2C_SCLin58NoneLVCMOS18I2C CLK / I2C CLK connected to module I2C interface 
I2C_SDAinout57NoneLVCMOS18I2C DATA/ I2C SDA connected to module I2C interface 
INIT
36--/ currently_not_used
JTAGENBin82NoneLVCMOS33Is used here to set bootmode JTAG(high) or QSPI(low)
LED1 / GLEDout4NoneLVCMOS33green LED D2
LED2 / RLEDout3NoneLVCMOS33red LED  D1
M_TCKin91NoneLVCMOS33CPLD JTAG B2B 
M_TDIin94NoneLVCMOS33CPLD JTAG B2B
M_TDOout95NoneLVCMOS33CPLD JTAG B2B
M_TMSin90NoneLVCMOS33CPLD JTAG B2B 
MIO8in38UPLVCMOS33used UART RS activity
MIO9out39NoneLVCMOS33User IO, connected to BOOTMODE Pin on B2B
MMC_RSTout40NoneLVCMOS33eMMC Reset
N.C. / dummy
1--/ currently_not_used
N.C.
2--/ currently_not_used
N.C.
27--/ currently_not_used
N.C.
28--/ currently_not_used
N.C.
29--/ currently_not_used
N.C.
30--/ currently_not_used
N.C.
32--/ currently_not_used
N.C.
41--/ currently_not_used
N.C.
42--/ currently_not_used
N.C.
59--/ currently_not_used
N.C.
60--/ currently_not_used
N.C.
61--/ currently_not_used
N.C.
62--/ currently_not_used
N.C.
63--/ currently_not_used
N.C.
64--/ currently_not_used
N.C.
65--/ currently_not_used
N.C.
66--/ currently_not_used
N.C.
67--/ currently_not_used
N.C.
68--/ currently_not_used
N.C.
69--/ currently_not_used
N.C.
70--/ currently_not_used
N.C.
71--/ currently_not_used
N.C.
74--/ currently_not_used
N.C.
75--/ currently_not_used
N.C.
76--/ currently_not_used
N.C.
77--/ currently_not_used
N.C.
78--/ currently_not_used
N.C.
81--/ currently_not_used
N.C.
83--/ currently_not_used
N.C.
84--/ currently_not_used
N.C.
85--/ currently_not_used
N.C.
86--/ currently_not_used
N.C.
87--/ currently_not_used
N.C.
88--/ currently_not_used
N.C.
89--/ currently_not_used
N.C.
96--/ currently_not_used
OTG-RSTout52UPLVCMOS18OTG Rest
OTG-RST33in45UPLVCMOS33OTG Reset from MIO0
PG_1.0V_MGTin19UPLVCMOS33Power control
PG_1.2V_MGTin17UPLVCMOS33Power control
PG_1.8Vin14UPLVCMOS33Power control
PG_1Vin25UPLVCMOS33Power control
PG_1V5in24UPLVCMOS33Power control
PG_3.3Vin13UPLVCMOS33Power control
PROG_B
35None-/ currently_not_used
PS_PORout37NoneLVCMOS33PS_POR_B (Power On Reset)
PS_SRSTout51NoneLVCMOS18PS_SRST_B (PS Reset)
RESINin97UPLVCMOS33Reset from B2B
RTC_INT
31--/ currently_not_used


Functional Description

JTAG

Used only for Firmware Update. Zynq has dedicated JTAG connection.

Power

Power enables (EN_1V, EN_1V8, EN_3V3, EN_1V2_MGT, EN_1V0_MGT) are all enabled sequentially.
EN_1V → EN_1V8 → EN_3V3 → EN_1V0_MGT → EN_1V2_MGT

Power goods (PG_1V, PG_1V5, PG_1V8, PG_3V3, PG_1V2_MGT, PG_1V0_MGT) are used for System Reset and LED Monitoring.

Boot Mode

JTAG or QSPI.
Bootmode is read through JTAGENB signal (can be set by DIP switch on carrier).
Can also be changed through software I2C after linux has bootet. (command: i2cset -y 0 0x20 0x03 <0x02 or 0x00>)

Reset

PS_POR is triggered by soft_resetn when bootmode is changed by software (I2C interface) or main power failed

PS_SRST is triggered when user reset pressed (RESIN) or main power failed.

ETH1_RESET is triggered when ETH1_RESET33(e.g. by fsbl) or main power failed.

OTG_RST is triggered when ETH1_OTG_RST33(e.g. by fsbl) or main power failed.

MMC_RST is triggered when main power failed.

main power failed

main power failed - is triggered when at least one of the Power Good signals of the DCDCs goes down.

UART

MIO8 is connected to CONFIGX. UART TX from FPGA to RX XMOD.

BOOTMODE is connected to MIO9. UART RX.

LED

Red LED D1

Blink sequencePriorityConditionDescription

********

highestRESIN = LOW (low active)external reset "RESIN" is pressed
*******o

blink sequence not used
******oo

blink sequence not used
*****ooo
PG_1V or PG_1V5 or PG_1V8 or PG_3V3 is zeroOne of the Power Good Signals of internal Voltages DCDCs LOW
****oooo

blink sequence not used
***ooooo

blink sequence not used
**oooooo
PG_1V2_MGT or PG_1V0_MGT is zeroOne of the Power Good Signals of MGT Voltages DCDCs LOW

*ooooooo


DONE  = '0'FPGA not programmed, wrong Bootmode? Check JTAGENB signal.
No design on QSPI Flash?
continuously ONlowestsoftware controlled command:
i2cset -y 0 0x20 0x05 <0x00 or 0x01>
If none of the above condition is met

Green LED D2

Blink sequencePriorityConditionDescription

********

highestPG_1V or PG_1V5 or PG_1V8 or PG_3V3 or
PG_1V2_MGT or PG_1V0_MGT is zero
Power Good Signal of DCDCs deassertion occurred after power up.
 Look at content of power good register → i2cget -y 0 0x20 0x02
*******o

blink sequence not used
******oo

blink sequence not used
*****ooo

blink sequence not used
****oooo

blink sequence not used
***ooooo
bootmode was changed via I2C.command: i2cset -y 0 0x20 0x03 <0x02 or 0x00>
**oooooo

blink sequence not used

*ooooooo



blink sequence not used
UART activitylowestLED = MIO8If none of the above condition is met

I2C Interface

This subsystem provides 2 x 32-bit (8 x 8-bit) of general purpose parallel input and output (I/O) expansion for the I2C bus protocol.  Address of this module is 0x20. This module contains eight 8-bit registers for reading and writing (GPIO_register_1[7:0] to GPIO_register_1[31:24] and GPIO_register_2[7:0] to GPIO_register_2[31:24]) separately with address 0x00 to 0x07. These registers can be accessed with I2C commands in linux console or with i2c functions in FSBL code. To access these registers the following commands in linux console can be used:

  • To see the i2c bus addresses :                                     i2cdetect -y -r 0   
  • To read register of i2c to GPIO module:                            i2cget -y 0 0x20 <register address>     
  • To write data in a register of i2c to GPIO module:                 i2cset -y 0 0x20 <register address> <data>

All eight registers can be read, but only two of them can be written from the linux console. 

I2C RegisterpermissionsaddressfunctionI2C command
GPIO_register_1(7 downto 0)readable0x00contains the CPLD Firmware Revision (not the PCB revision)read: i2cget -y 0 0x20 0x00
GPIO_register_1(15 downto 8) readable0x01contains the bootmode in bit 8 and bit 9. This register is read by the fsbl and printed
in the console as the bootmode during power up

GPIO_register_1(23 downto 16)readable0x02Bit 17 to 23 contain the DCDC power good signals and the DONE pin
GPIO_register_1(31 downto 24)readable/writeable0x03Bit 24 and 25 contain the bootmode, JTAG(b 00) or QSPI(b 10)write: i2cset -y 0 0x20 0x03 <0x02 or 0x00>
GPIO_register_2(7 downto 0)readable0x04Bit 0 to 3 show the state of the reset signals PS_POR, PS_SRST, ETH1_RESET, OTG_RST
GPIO_register_2(15 downto 8)readable/writeable0x05Bit 8 can be controlled to change the state of the red LED D1 if no other red LED
condition is met
write: i2cset -y 0 0x20 0x05 <0x00 or 0x01>
GPIO_register_2(23 downto 16)readable0x06not used
GPIO_register_2(31 downto 24)readable0x07not used


Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescriptionFirmware release

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REV02.1REV02.1

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  • JTAGENB functionality inverted - "0" -> QSPI; "1" -> JTAG
Revision 02.1, 18.06.2024 released 



REV02REV02

 

  • CPLD Firmware Update
  • LED blinking


  • Power Sequencing 


  • I2C Interface to FPGA for status communication


Revision 02, 28.11.2023 released 

2018-05-25


v.5

 REV01 RE02

John

Hartfiel

 

  • typo correction
  • add UART description

v.3REV01RE02John Hartfiel
  • REV01 , Firmware released  2016-06-27

2018-03-12

v.1



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  • Initial release


All

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Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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