Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze is add for Hello TE0741 example.
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2018-06-22 | 2017.4 | TE0841-IBERT_noprebuilt-vivado_2017.4-build_11_20180622140813.zip TE0841-IBERT-vivado_2017.4-build_11_20180622140615.zip | John Hartfiel |
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2018-06-05 | 2017.4 | TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip | John Hartfiel |
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Issues | Description | Workaround | To be fixed version |
---|---|---|---|
PCB REV01 only: IBERT no CLK | PCB REV01 SI5338 is not preprogrammed and SI programming over MCS is disabled by default design and I2C is not connected | Load test_board bitfile for REV01 and load IBERT design again without power off HW | --- |
Software | Version | Note |
---|---|---|
Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
TE0841-01-035-1C | 01_35_1c | REV01 | 2x 512MB DDR4 | 32MB | --- | |
TE0841-01-035-1I | 01_35_1i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
TE0841-01-035-2I | 01_35_2i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
TE0841-01-040-1C | 01_40_1c | REV01 | 2x 512MB DDR4 | 32MB | --- | Serial number 512479 up tp 512474 has same 64MB Flash like REV02 |
TE0841-01-040-1I | 01_40_1i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
TE0841-01-040-2I | 01_40_2i | REV01 | 2x 512MB DDR4 | 32MB | --- | |
TE0841-02-035-1C | 02_35_1c | REV02 | 2x 1GB DDR4 | 64MB | --- | |
TE0841-02-035-1I | 02_35_1i | REV02 | 2x 1GB DDR4 | 64MB | --- | |
TE0841-02-035-2I | 02_35_2i | REV02 | 2x 1GB DDR4 | 64MB | --- | |
TE0841-02-040-1C | 02_40_1c | REV02 | 2x 1GB DDR4 | 64MB | --- | |
TE0841-02-040-1I | 02_40_1i | REV02 | 2x 1GB DDR4 | 64MB | --- | |
TE0841-02-040-1IL | 02_40_1i | REV02 | 2x 1GB DDR4 | 64MB | low profile B2B connector |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TEBA0841 | used as reference carrier |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
Heat sink | It's recommended to use heat sink for this design |
For general structure and of the reference design, see Project Delivery - AMD devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
Type | Location | Notes |
---|---|---|
SI5338 Project | \misc\SI5338 |
File | File-Extension | Description |
---|---|---|
BIT-File | *.bit | FPGA (PL Part) Configuration File |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:AMD Development Tools#XilinxSoftware-BasicUserGuides
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used on this Example.
IBERT | Component Name | Net Name | TEB0841 |
---|---|---|---|
X0Y0 | 224-0 | MGT4 | loop back RX/TX |
X0Y1 | 224-1 | MGT5 | loop back RX/TX |
X0Y2 | 224-2 | MGT6 | loopback over SD Pin header possible with lower Linerate otherwise use internal loopback |
X0Y3 | 224-3 | MGT7 | loop back RX/TX. Note: N.C. on TEB0841-01, use internal loopback |
X0Y4 | 225-0 | MGT0 | loop back RX/TX |
X0Y5 | 225-1 | MGT1 | loop back RX/TX |
X0Y6 | 225-2 | MGT2 | loop back RX/TX |
X0Y7 | 225-3 | MGT3 | loopback over sfp possible |
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design] set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# file: ibert_ultrascale_gth_0.xdc #################################################################################### ## ____ ____ ## / /\/ / ## /___/ \ / Vendor: Xilinx ## \ \ \/ Version : 2012.3 ## \ \ Application : IBERT Ultrascale ## / / Filename : example_ibert_ultrascale_gth_0.xdc ## /___/ /\ ## \ \ / \ ## \___\/\___\ ## ## ## ## Generated by Xilinx IBERT 7Series ##************************************************************************** ## ## Icon Constraints ## create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i] set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub] ##gth_refclk lock constraints ## set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]] set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]] set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]] set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]] ## ## Refclk constraints ## create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]] create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]] set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous ## ## System clock pin locs and timing constraints ## #set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i] #set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]
For SDK project creation, follow instructions from:
MCS Firmware to configure SI5338 and Reset System.
Template location: \sw_lib\sw_apps\scu
Download ClockBuilder Desktop for SI5338
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
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v.5 | John Hartfiel |
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v.4 | John Hartfiel |
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2018-04-16 | v.1 |
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All |
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