Quick Start
The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.
The "normal" Quartus project will be generated in the subfolder "/quartus/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.
There are several options to create the Quartus project from the project delivery.
One option to create project ist using the "Module Selection Guide" in "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS:
- Execute "_create_win_setup.cmd" or "_create_linux_setup.sh"
- Select "Module Selection Guide" (press "0" and Enter)
- Follow instructions
For manuell configuration or addition command files for execution will be generated with "_create_win_setup.cmd" or "_create_linux_setup.sh". If you use our prepared batch files for project creation do the following steps:
- open "design_basic_settings.cmd/.sh" with text editor and set correct quartus path and board part number from <project_root_directory>/board_files/TEIxxxx_devices.csv
- run "quartus_create_project_batchmode.cmd/sh".
See Reference Design: Getting Started for more details.
Zip Project Delivery
Zip Name Description
Description | PCB Name |
| Project Name+(opt. Variant) |
| supported Quartus Version |
| Date |
|
---|
Example: | TEI0001 | - | test_board(_noprebuilt) | - | quartus_18.1 | - | 20191024100836 | .zip |
Last supported Release
Type or File | Version |
---|
Quartus Prime | 18.1 |
Trenz Project Scripts | 18.1.00 |
Trenz <board_series>_devices.csv | 1.0 |
Trenz zip_ignore_list.csv | 1.0 |
Trenz mod_list.csv | 1.0 |
Currently limitations of functionality
- no current limitations of functionality
Directory structure
File or Directory | Type | Description |
---|
<design_name> | work, base directory | Base directory with predefined batch files (*.cmd) to generate or open Quartus-Project |
<design_name>/backup/ | generated | (Optional) Directory for project backups |
<design_name>/board_files/ | source | Local list of available board variants (<board_series>_devices.csv) |
<design_name>/console | source | Folder with different command files. Use _create_win_setup.cmd to generate files on top folder |
<design_name>/log/ | generated | (Temporary) Directory with quartus log files (used only with predefined commands from tcl scripts, otherwise this logs will be writen into the Quartus working directory) |
<design_name>/prebuilt/ | prebuilt | Contains subfolders for different board variants |
<design_name>/prebuilt/<board_part_shortname> | prebuilt | Directory with prebuilt programming files (*.pof) for FPGA and different source files for hardware (*.sopcinfo) and software (*.elf) included in subfolders |
<design_name>/prebuilt/<board_part_shortname>/programming_files/ | prebuilt | Directory with prebuilt programming files (*.pof) |
<design_name>/prebuilt/<board_part_shortname>/hardware/ | prebuilt | Directory with prebuilt hardware sources (*.sopcinfo) |
<design_name>/prebuilt/<board_part_shortname>/software/ | prebuilt | Directory with prebuilt software sources (*.elf) |
<design_name>/quartus/ | generated | (Temporary) Directory where Quartus project is created. Quartus project file is <design_name>.qpf |
<design_name>/scripts/ | source | TCL scripts to build a project |
<design_name>/settings/ | source | (Optional) Additional design settings: zip_ignore_list.csv, mod_list.csv, preset_qsys.qprs |
<design_name>/software/ | generated | (Temporary) Directory with additional software |
<design_name>/source_files/ | source | Directory with source files needed for creating project
|
<design_name>/source_files/quartus/ | source | Source files for Quartus project |
<design_name>/source_files/software/ | source | Source files for additional software |
Command Files
Command files will be generated with "_create_win_setup.cmd" on Windows OS and with "_create_linux.setup.sh" on Linux OS.
Windows Command Files
File Name | Description |
---|
Design + Settings |
_create_win_setup.cmd | Use to create batch files or project with "Module Selection Guide". |
design_basic_settings.cmd | Settings for the other *.cmd files. Following settings are avaliable: - General Settings:
- (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
- Intel settings:
- QUADIR: Set Intel installation path (default: C:/intelFPGA_lite).
- QUARTUS_VERSION: Current Quartus Version (default: 18.1). Don't change Quartus Version.
- Board Setting:
- PARTNUMBER: Set Board part number of the project which should be created
- Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from <design_name>/board_files/TEIxxxx_devices.csv list)
- Used for project creation and programming
- Example TEI0001 Module :
- Use ID → PARTNUMBER=1
- Use PRODID → PARTNUMBER=TEI0001-02-08-C8
|
Hardware Design |
quartus_create_project_batchmode.cmd | Create Project with settings from "design_basic_settings.cmd" and source folders. Build all Quartus hardware and software files if the sources are available. If old quartus project exists, type "y" into the command line input to delete "<design_name>/quartus/", and "<design_name>/software/" directory with related files before project will created again. |
quartus_open_existing_project_guimode.cmd | Opens an existing Project from "<design_name>/quartus/<design_name>.qpf" |
Linux Command Files
File Name | Description |
---|
Design + Settings |
_create_linux_setup.sh | Use to create bash files or project with "Module Selection Guide". |
design_basic_settings.sh | Settings for the other *.sh files. Following settings are avaliable: - General Settings:
- (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
- Intel settings:
- QUADIR: Set Intel installation path (default: ~/intelFPGA_lite).
- QUARTUS_VERSION: Current Quartus Version (default: 18.1). Don't change Quartus Version.
- Board Setting:
- PARTNUMBER: Set Board part number of the project which should be created
- Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from <design_name>/board_files/TEIxxxx_devices.csv list)
- Used for project creation and programming
- Example TEI0001 Module :
- Use ID → PARTNUMBER=1
- Use PRODID → PARTNUMBER=TEI0001-02-08-C8
|
Hardware Design |
quartus_create_project_bashmode.sh | Create Project with settings from "design_basic_settings.sh" and source folders. Build all Quartus hardware and software files if the sources are available. If old quartus project exists, type "y" into the command line input to delete "<design_name>/quartus/", and "<design_name>/software/" directory with related files before project will created again. |
quartus_open_existing_project_guimode.sh | Opens an existing Project from "<design_name>/quartus/<design_name>.qpf" |
Design Environment: Usage
Reference-Design: Getting Started
- Install "Quartus Prime 18.1 Lite Edition" (additional recommended: Install "Quartus Prime Software v18.1 Update 1")
- Automatically configuration of the reference-designs:
- Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
- select "Module Selection Guide" and follow instructions.
- "design_basic_settings.cmd/.sh" will be configured over this menu
- Manual Configure the reference-design (Note: batch/bash files works only in the basefolder of the project, use "_create_win_setup.cmd"/"_create_linux_setup.sh" or copy manually):
1. Open “design_basic_settings.cmd/.sh” with a text-editor:
a. Set correct Quartus Environment:
@set QUADIR=C:/intelFPGA_lite (example for Windows OS)
@set QUARTUS_VERSION=18.1
Program settings will be search in :
%QUADIR%/%QUARTUS_VERSION%/quartus/
%QUADIR%/%QUARTUS_VERSION%/nios2eds/
Example directory: C:/intelFPGA_lite/18.1/
Attention: Scripts are supported only with predefined Quartus Version!
b. Set the correct module part-number:
@set PARTNUMBER=x
You find the available Module Numbers in <design_name>/board_files/TEIxxxx_devices.csv
- Create a project in one step:
2. Run “quartus_create_project_batchmode.cmd”/"quartus_create_project_bashmode.sh" - Programming FPGA or flash memory with prebuilt files:
3. Connect your Hardware-Modul with PC via JTAG
4. Open "Programmer (Quartus Prime 18.1)" from start menu or run "quartus_open_existing_project_guimode.cmd" and select Tools → Programmer
5. Select "Add File..." and open correct file from <design_name>/prebuilt/<board_part_shortname>/programming_files/
6. Press "Start" to programm FPGA or flash memory
Hardware Design
Device list CSV Description
Device list csv file is used for TE-Scripts only.
Name | Description | Value |
---|
ID | ID to identify the board variant of the module series, used in TE-Scripts | Number, should be unique in csv list |
PRODID | Product ID | Product Name |
FAMILY | FPGA family, used in Quartus and TE-Scripts | device family, which is available in Quartus, ex. MAX 10 |
DEVICE | FPGA device, used in Quartus and TE-Scripts | device, which is available in Quartus, ex. 10M08SAU169C8G |
SHORTNAME | Subdirectory name, used for multi board projects to get correct sources and save prebuilt data | name to save prebuilt files or search for sources |
FLASHTYP | Flash typ used for programming Devices via Quartus/LabTools | "<Flash Name from Quartus>|<SPI Interface>" or "NA" , NA is not defined |
FLASH_SIZE | Size of Module Flash | use MB, for ex. "64MB" or "NA" if not available |
DDR_DEV | DDR Module | DDR module name |
DDR_SIZE | Size of Module DDR | use GB or MB, for ex. "2GB" or "512MB" or "NA" if not available |
PCB_REV | Supported PCB Revision | "<supported PCB Revision>|<supported PCB Revision>", for ex. "REV02" or "REV03|REV02" |
SDC Conventions
- All *.sdc from <design_name>/source_files/quartus/ are load into the quartus project on project creation.
Advanced Usage
Attention not all features of the TE-Scripts are supported in the advanced usage!
User defined device list csv file
To modifiy current device list csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TEI0001_devices.csv as TEI0001_devices_mod.csv. Scripts use modified csv instead of the original file.
User defined Settings
ZIP ignore list:
Files which should not be added in the backup file can be defined in this file: "<design_name>/settings/zip_ignore_list.csv". This file will be loaded automaticaly on script initialisation.
mod list:
List with commands to modify source files during project creation. (<design_name>/settings/mod_list.csv)
Qsys presets file:
Predefined settings for Qsys IP Components (<design_name>/settings/presets_qsys.qprs)
HDL-Design
HDL files can be saved in the subfolder "<design_name>/vhdl/". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.
Checklist / Troubleshoot
- Are you using exactly the same Quartus version? If not then the scripts will not work, no need to try.
- Are you using Quartus on Windows PC? Quartus works in Linux also, but the scripts are tested on Windows only.
- Win OS only: Use short path name, OS allows only 256 characters in normal path.
- Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be display: /bin/sh -> bash. Access rights can be changed with "chmod"
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation problem) and the scripts canceled. Please try again.
- If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design.
References
- Intel Quartus Prime User Guide: Getting Started (UG-20129)
- Intel Quartus Prime User Guide: Platform Designer (UG-20130)
- Intel Quartus Prime User Guide: Design Compilation (UG-20132)
- Intel Quartus Prime User Guide: Scripting (UG-20144)
Document Change History
To get content of older revision got to "Change History" of this page and select older revision number.
Date | Revision | Quartus Version | Authors | Description |
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Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission.
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[interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission.
Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between:
[interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
[interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] | 18.1 | Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission.
Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between:
[interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
[interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
| - add description for *.sh files (Linux OS)
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2019-10-29 | v.4 | 18.1 | Thomas Dück | |
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| Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission.
Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between:
[interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
[interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]
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