F32C BRAM SoC
This is mainly IP Core wrap around "bram glue" generic F32C SoC RTL, Changes to orginal RTL include change of the GPIO IP Core to export the tri-state bus to toplevel as 3 signals, no inout ports used any more.
Getting this Design ported to any new board usually takes less than 5 minutes. So far all newly ported design for new boards have worked first time tested with 0 time wasted in debug or troubleshooting.
F32C Core
Overview
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