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Overview

The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020).

This SoM has following peripherals on board:

  • 1 x Gbps Ethernet Phy transceiver
  • 2 x 100 Mbps Ethernet PHY transceivers
  • 512 MByte DDR3 SDRAM
  • 32 MByte Flash-Memory
  • 4 Gbyte e-NAND-Flash-Memory
  •  USB PHY transceiver
  • powerful switch-mode power supplies for all on-board voltages
  • large number of configurable I/Os is provided via rugged high-speed stacking strips

All modules in 4 x 5 cm form factor are mechanically compatible.

Block diagram

Board Components

Main Components:

Key Features

  • Industrial-grade Xilinx Zynq-7000 (XC7Z020) SoM
  • Rugged for shock and high vibration
  • 2 x ARM Cortex-A9
  • 1 x 10/100/1000 Mbps Ethernet transceiver PHY
  • 2 x 10/100 Mbps Ethernet transceiver PHYs
  • 3 x MAC-Address EEPROMs
  • 16-Bit wide 512 MByte DDR3 SDRAM
  • 32 MByte QSPI-Flash-Memory
  • 4 GByte e-NAND-Flash-Memory (embedded eMMC Memory)
  • USB 2.0 high-speed ULPI transceiver
  • Plug-on module with 2 x 120-pin high-speed hermaphroditic strips
  • 136 FPGA I/Os (58 LVDS pairs possible) and 6 PS MIOs available on board-to-board connectors
  • On-board high-efficiency DC-DC converters
    • 4.0 A x 1.0 V power rail
    • 1.5 A x 1.5 V power rail
    • 1.5 A x 1.8 V power rail
    • 1.5 A x 2.5 V power rail
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • User LED
  • Evenly-spread supply pins for good signal integrity

Assembly options for cost or performance optimization available upon request.

 

Signals, Interfaces and Pins

System Controller I/O Pins

Special purpose pins used by TE0729

NameNote
NRST 
NRST_IN 

Boot Modes

By default the TE-0729 supports QSPI-Flash-Memory, JTAG and SD-Card (if available on base board) boot modes.

The boot modes are controlled by the Pins 'BOOT1' and 'BOOT2' on the board to board (B2B) connector.

Pin-State

BOOTMODE1 / BOOTMODE2

boot mode
LOW / LOW 
LOW / HIGH 
HIGH / LOW 
HIGH / HIGH 

JTAG

JTAG access to the Xilinx Zynq-7000 device is provided by connector J2.

SignalB2B Pin
TCKJ2:  119
TDIJ2:  115
TDOJ2:  117
TMSJ2:  113

JTAGSEL pin in J2 should be kept low or grounded for normal operation.

 

Clocking

ClockFrequencyICFPGANotes
PS CLK33.3333 MHzU14PS_CLKPS Subsystem main clock
10/100/1000 Mbps ETH PHY reference25 MHzU10- 
USB PHY reference52 MHzU12- 

 

Processing System (PS) Peripherals

PeripheralICDesignatorPSMIONotes
EEPROM I2C24AA025E48T-I/OTU8I2C0MIO10, MIO11MAC1-Adress
EEPROM I2C24AA025E48T-I/OTU9I2C0MIO10, MIO11MAC2-Adress
EEPROM I2C24AA025E48T-I/OTU20I2C0MIO10, MIO11MAC3-Adress
RTCISL12020MIRZU22I2C0MIO10, MIO11Temperature compensated real time clock
RTC InterruptISL12020MIRZU22GPIOMIO46Real Time Clock Interrupt
SPI FlashS25FL256SAGBHI20U13QSPI0MIO1..MIO6 
Ethernet 10/100/1000 Mbps PHY88E1512-A0-NNP2I000U3ETH0MIO16...MIO27 
Ethernet 10/100/1000 Mbps PHY Reset  GPIOMIO51 
Ethernet1 10/100 Mbps PHYKSZ8081MLXCAU17GPIO BANK34 I/O (IO_L1_P/N_T0_34 ... IO_L24_P/N_T3_34)
Ethernet1 10/100 Mbps PHY Reset  GPIO IO_L19N_T3_VREF_34
Ethernet2 10/100 Mbps PHYKSZ8081MLXCAU19GPIO BANK34 I/O (IO_L1_P/N_T0_34 ... IO_L24_P/N_T3_34)
Ethernet2 10/100 Mbps PHY Reset  GPIO IO_LP_T0_34
USBUSB3320C-EZKU11USB0 MIO28...MIO39 
USB Reset  GPIOMIO49 
 e-NAND-Flash-Memory (embedded e-MMC)MTFC4GMVEA-4M IT  U5GPIOMIO40...MIO45depending on state of pin MIO48 'SEL_SD'

 

Default MIO mapping:

MIOConfigured asB2BNotes
    
    
    
    
    
    

 

 

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