Overview
The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020).
This SoM has following peripherals on board:
- 1 x Gbps Ethernet Phy transceiver
- 2 x 100 Mbps Ethernet PHY transceivers
- 512 MByte DDR3 SDRAM
- 32 MByte Flash-Memory
- 4 Gbyte NAND-Flash-Memory
- USB PHY transceiver
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
All modules in 4 x 5 cm form factor are mechanically compatible.
Block diagram
Board Components
Main Components:
Key Features
- Industrial-grade Xilinx Zynq-7000 (XC7Z020) SoM
- Rugged for shock and high vibration
- 2 x ARM Cortex-A9
- 1 x 10/100/1000 Gbps Ethernet transceiver PHY
- 2 x 10/100 Mbps Ethernet transceiver PHYs
- 3 x MAC-Address EEPROMs
- 16-Bit wide 512 MByte DDR3 SDRAM
- 32 MByte QSPI-Flash-Memory
- 4 GByte NAND-Flash-Memory (embedded eMMC Memory)
- USB 2.0 high-speed ULPI transceiver
- Plug-on module with 2 x 120-pin high-speed hermaphroditic strips
- 136 FPGA I/Os (58 LVDS pairs possible) and 6 PS MIOs available on board-to-board connectors
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- 1.5 A x 2.5 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
Signals, Interfaces and Pins
System Controller I/O Pins
Special purpose pins used by TE0729
| Name | Note |
|---|---|
| NRST | |
| NRST_IN |
Boot Modes
By default the TE-0729 supports QSPI-Flash-Memory, JTAG and SD-Card (if available on base board) boot modes.
The boot modes are controlled by the Pins 'BOOT1' and 'BOOT2' on the board to board (B2B) connector.
Pin-State BOOTMODE1 / BOOTMODE2 | boot mode |
|---|---|
| LOW / LOW | |
| LOW / HIGH | |
| HIGH / LOW | |
| HIGH / HIGH |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided by connector J2.
| Signal | B2B Pin |
|---|---|
| TCK | J2: 119 |
| TDI | J2: 115 |
| TDO | J2: 117 |
| TMS | J2: 113 |
JTAGEN pin in JM1 should be kept low or grounded for normal operation.
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
| 10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
| USB PHY reference | 52 MHz | U12 | - |
Processing System (PS) Peripherals
| Peripheral | IC | Designator | PS | MIO | Notes |
|---|---|---|---|---|---|
| EEPROM I2C | 24AA025E48T-I/OT | U8 | I2C0 | MIO10, MIO11 | MAC1-Adress |
| EEPROM I2C | 24AA025E48T-I/OT | U9 | I2C0 | MIO10, MIO11 | MAC2-Adress |
| EEPROM I2C | 24AA025E48T-I/OT | U20 | I2C0 | MIO10, MIO11 | MAC3-Adress |
| RTC | ISL12020MIRZ | U22 | I2C0 | MIO10, MIO11 | Temperature compensated real time clock |
| RTC Interrupt | ISL12020MIRZ | U22 | GPIO | MIO46 | Real Time Clock Interrupt |
| SPI Flash | |||||
| Ethernet | |||||
| USB | |||||
| LED | |||||
| USB Reset | |||||
Ethernet Reset |
Default MIO mapping:
| MIO | Configured as | B2B | Notes |
|---|---|---|---|
Overview
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