Overview
The Trenz Electronic TE0729 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020).
This SoM has following peripherals on board:
- 1 x Gbps Ethernet Phy transceiver
- 2 x 100 Mbps Ethernet PHY transceivers
- 512 MByte DDR3 SDRAM
- 32 MByte Flash-Memory
- 4 Gbyte e-NAND-Flash-Memory
- USB PHY transceiver
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
All modules in 4 x 5 cm form factor are mechanically compatible.
Block diagram
Board Components
Main Components:
Key Features
- Industrial-grade Xilinx Zynq-7000 (XC7Z020) SoM
- Rugged for shock and high vibration
- 2 x ARM Cortex-A9
- 1 x 10/100/1000 Mbps Ethernet transceiver PHY
- 2 x 10/100 Mbps Ethernet transceiver PHYs
- 3 x MAC-Address EEPROMs
- 16-Bit wide 512 MByte DDR3 SDRAM
- 32 MByte QSPI-Flash-Memory
- 4 GByte e-NAND-Flash-Memory (embedded eMMC Memory)
- USB 2.0 high-speed ULPI transceiver
- Plug-on module with 2 x 120-pin high-speed hermaphroditic strips
- 136 FPGA I/Os (58 LVDS pairs possible) and 6 PS MIOs available on board-to-board connectors
- On-board high-efficiency DC-DC converters
- 4.0 A x 1.0 V power rail
- 1.5 A x 1.5 V power rail
- 1.5 A x 1.8 V power rail
- 1.5 A x 2.5 V power rail
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
Signals, Interfaces and Pins
System Controller I/O Pins
Special purpose pins used by TE0729
| Name | Note |
|---|---|
| NRST | |
| NRST_IN |
Boot Modes
TE0729 supports primary boot from
- JTAG
- SPI Flash
- SD Card
Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).
The boot modes are controlled by the Pins 'BOOT1' and 'BOOT2' on the board to board (B2B) connector.
BOOTMODE1 | BOOTMODE2 | Boot mode |
|---|---|---|
| LOW | LOW | |
| LOW | HIGH | |
| HIGH | LOW | |
| HIGH | HIGH |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided by connector J2.
| Signal | B2B Pin |
|---|---|
| TCK | J2: 119 |
| TDI | J2: 115 |
| TDO | J2: 117 |
| TMS | J2: 113 |
JTAGSEL pin in J2 should be kept low or grounded for normal operation.
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
| PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
| 10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
| USB PHY reference | 52 MHz | U12 | - |
Processing System (PS) Peripherals
| Peripheral | IC | Designator | PS | MIO | Notes |
|---|---|---|---|---|---|
| EEPROM I2C | 24AA025E48T-I/OT | U8 | I2C0 | MIO10, MIO11 | MAC Address |
| EEPROM I2C | 24AA025E48T-I/OT | U9 | I2C0 | MIO10, MIO11 | MAC Address |
| EEPROM I2C | 24AA025E48T-I/OT | U20 | I2C0 | MIO10, MIO11 | MAC Address |
| RTC | ISL12020MIRZ | U22 | I2C0 | MIO10, MIO11 | Temperature compensated real time clock |
| RTC Interrupt | ISL12020MIRZ | U22 | GPIO | MIO46 | Real Time Clock Interrupt |
| SPI Flash | S25FL256SAGBHI20 | U13 | QSPI0 | MIO1..MIO6 | |
| Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U3 | ETH0 | MIO16...MIO27 | |
| Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO51 | |||
| Ethernet1 10/100 Mbps PHY | KSZ8081MLXCA | U17 | - | (EMIO) | |
| Ethernet1 10/100 Mbps PHY Reset | - | (EMIO) | |||
| Ethernet2 10/100 Mbps PHY | KSZ8081MLXCA | U19 | - | (EMIO) | |
| Ethernet2 10/100 Mbps PHY Reset | - | (EMIO) | |||
| USB | USB3320C-EZK | U11 | USB0 | MIO28...MIO39 | |
| USB Reset | GPIO | MIO49 | |||
| e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U5 | SDIO0 | MIO40...MIO45 | depending on state of pin MIO48 'SEL_SD' |
Default MIO mapping:
| MIO | Configured as | B2B | Notes |
|---|---|---|---|
| 0 | GPIO | J2-87 | B2B |
| 1 | QSPI0 | - | SPI Flash-CS |
| 2 | QSPI0 | - | SPI Flash-DQ0 |
| 3 | QSPI0 | - | SPI Flash-DQ1 |
| 4 | QSPI0 | - | SPI Flash-DQ2 |
| 5 | QSPI0 | - | SPI Flash-DQ3 |
| 6 | QSPI0 | - | SPI Flash-SCK |
| 7 | GPIO | - | Red LED D8 |
| 8 | - | - | - |
| 9 | GPIO | J2-88 | B2B |
| 10 | I2C0 SDA | J2-90 | B2B |
| 11 | I2C0 SCL | J2-92 | B2B |
| 12 | I2C1 SDA | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) |
| 13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) |
| 14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) |
| 15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) |
| 16..27 | ETH0 | RGMII | |
| 28..39 | USB0 | ULPI | |
| 40 | SDIO0 | J2-100 | B2B depending on state of pin MIO48 'SEL_SD' |
| 41 | SDIO0 | J2-102 | B2B depending on state of pin MIO48 'SEL_SD' |
| 42 | SDIO0 | J2-104 | B2B depending on state of pin MIO48 'SEL_SD' |
| 43 | SDIO0 | J2-106 | B2B depending on state of pin MIO48 'SEL_SD' |
| 44 | SDIO0 | J2-108 | B2B depending on state of pin MIO48 'SEL_SD' |
| 45 | SDIO0 | J2-110 | B2B depending on state of pin MIO48 'SEL_SD' |
| 46 | GPIO | - | RTC Interrupt |
| 47 | - | - | - |
| 48 | GPIO | SEL_SD | select source between e-MMC / baseboard SD-Card |
| 49 | GPIO | - | USB Reset |
| 50 | GPIO | - | ETH0 Interrupt |
| 51 | GPIO | - | ETH0 Reset |
| 52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
Overview
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