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| Number/Link | Description |
|---|
| AR# 66652 | Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Base TRD Monitor requirements |
| AR# 68006 | Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly |