The Trenz Electronic TE0710 is an industrial-grade FPGA module integrating a Xilinx Artix-7 T FPGA, dual 100 MBit Ethernet transceivers, 512 MByte DDR3 SDRAM with 8-bit width, 32 megabyte Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
All this on a tiny footprint, smaller than a credit card, at the most competitive price.
Industrial-grade Xilinx Artix-7 (15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool
Rugged for shock and high vibration
512 MByte DDR3 SDRAM
Dual 100 MBit Ethernet PHY
MAC Address EEPROM
32 MByte QSPI Flash memory (with XiP support)
100 MHz programmable MEMS oscillator
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
112 FPGA I/Os (51 differential pairs) and available on board-to-board connectors
On-board high-efficiency DC-DC converters
4.0 A x 1.0 V power rail
1.0 A x 1.8 V power rail
1.0 A x 1.5 V power rail
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
The TE0710 board is populated with the Artix-7 Series Families FPGA. The devices can be programmed with the free Xilinx Vivado WebPACK software. Further information on the Artix-7 FPGA can be found in the Xilinx document 7 Series FPGAs Overview (DS180).
The following two FPGA configuration interfaces are supported:
For debugging purposes
SPI Master 4-bit mode
Main configuration mode: 4-Bit mode must be used when generating bitstream
|CFGBVS||3.3V||Select 3.3V as Config Bank I/O Voltage|
|PUDC||Strong pull-up to 3.3V||Pre-configuration pull-ups are DISABLED|
Memory size (MBytes)
Value to be used with Vivado labtools flash programmer
Vivado Board Part File Interface name
Parameter values for the SPI Flash memory included in the standard assembly option.
The TE0710 board has a 3.3V single ended 100MHz oscillator (U8). It is wired to an FPGA MRCC clock input on bank 35.
Oscillator: Si Time SiT8008AI-73-XXS-100.000000E (100 MHz)
Frequency stability: 50 ppm
Vivado Board Part Interface
|Power On Reset||System Controller||PROG_B released after power on causing FPGA reconfiguration|
|Config Reset||JM2.18||Active low value forces FPGA reconfiguration|
|Dummy Reset||FPGA pin D9||Can be used as reset with fixed always inactive value if needed (may have to add pullup or pulldown constraint)|
|Soft Reset||Any FPGA B2B I/O||User defined soft reset input with user defined polarity|
|Debug Reset||Microblaze MDM||JTAG debugger soft reset|
The TE0710 board has 3 LEDs. One is user led, which is connected to Pin L15 on the Bank 14. The other two are connected to the system controller.
System controller status LED
System controller status LED
User LED, active LOW
|Signal||B2B Module||B2B Base||Description|
|JTAGSEL||JM1: 89||keep low or GND for normal operation|
The TE0710 board contains one DDR3 component with a capacity of 4Gb.
- Part number: MEM4G08D3EABG-125 (Memphis)
- Supply voltage: 1.5V
- Organization: 64M words x 8 bits x 8 banks
- Memory speed limited by Artix speed grade and MIG
Configuration of the DDR3 memory controller in the FPGA should be done using the Xilinx MIG tool in the Vivado IP catalog. Refer to the reference design section (DDR3 Reference Design) for information on how to do this.
DDR3 Memory Connections to the FPGA
|FPGA Pin||FPGA Bank||I/O Standard||Comment|
|D3||35||SSTL15||DDR3 Address 0|
|B2||35||SSTL15||DDR3 Address 1|
|G1||35||SSTL15||DDR3 Address 2|
|D4||35||SSTL15||DDR3 Address 3|
|E1||35||SSTL15||DDR3 Address 4|
|D2||35||SSTL15||DDR3 Address 5|
|F1||35||SSTL15||DDR3 Address 6|
|D5||35||SSTL15||DDR3 Address 7|
|C1||35||SSTL15||DDR3 Address 8|
|B3||35||SSTL15||DDR3 Address 9|
|E3||35||SSTL15||DDR3 Address 10|
|A1||35||SSTL15||DDR3 Address 11|
|E2||35||SSTL15||DDR3 Address 12|
|B4||35||SSTL15||DDR3 Address 13|
|C2||35||SSTL15||DDR3 Address 14|
|H1||35||SSTL15||DDR3 Address 15|
|C5||35||SSTL15||DDR3 Data 0|
|B7||35||SSTL15||DDR3 Data 1|
|B6||35||SSTL15||DDR3 Data 2|
|C6||35||SSTL15||DDR3 Data 3|
|C7||35||SSTL15||DDR3 Data 4|
|D8||35||SSTL15||DDR3 Data 5|
|E5||35||SSTL15||DDR3 Data 6|
|E7||35||SSTL15||DDR3 Data 7|
|A6||35||DIFF_SSTL15||DDR3 Data Strobe|
|A5||35||DIFF_SSTL15||DDR3 Data Strobe|
|E6||35||SSTL15||DDR3 Data Mask|
Ethernet PHY Connections
|FPGA Pin||FPGA Bank||Net Name||I/O Standard||Comment|
|U14||14||ETH-RST||LVCMOS33||Ethernet Reset, active-low|
|T14||14||ETH_TXCLK||LVCMOS33||Ethernet transmit clock input from PHY|
|R16||14||ETH_TX_D0||LVCMOS33||Ethernet transmit data 0. Output to Ethernet PHY.|
|U18||14||ETH_TX_D1||LVCMOS33||Ethernet transmit data 1. Output to Ethernet PHY.|
|14||ETH_TX_D2||LVCMOS33||Ethernet transmit data 2. Output to Ethernet PHY.|
|R17||14||ETH_TX_D3||LVCMOS33||Ethernet transmit data 3. Output to Ethernet PHY.|
|R15||14||ETH_TX_EN||LVCMOS33||Ethernet transmit enable. Output to Ethernet PHY.|
|N15||14||ETH_RXCLK||LVCMOS33||Ethernet receive clock input from PHY.|
|U12||14||ETH_RX_D0||LVCMOS33||Ethernet receive data 0. Input from Ethernet PHY.|
|V12||14||ETH_RX_D1||LVCMOS33||Ethernet receive data 1. Input from Ethernet PHY.|
|U13||14||ETH_RX_D2||LVCMOS33||Ethernet receive data 2. Input from Ethernet PHY.|
|T15||14||ETH_RX_D3||LVCMOS33||Ethernet receive data 3. Input from Ethernet PHY.|
|V10||14||ETH_RX_DV||LVCMOS33||Ethernet receive data valid. Input from Ethernet PHY.|
|V11||14||ETH_RX_ER||LVCMOS33||Ethernet receive error. Input from Ethernet PHY.|
Ethernet collision detect input from Ethernet PHY.
Ethernet power down or interrupt.
(default function is power down)
Ethernet LED Pin to indicate status. Mode 1: LINK Indication LED; Mode 2: ACT Indication LED
|T13||14||MDC||LVCMOS33||Ethernet to PHY MII Management clock|
|V14||14||MDIO||LVCMOS33||PHY MDIO data I/O ( 3-state buffer)|
|P17||14||ETH2_TXCLK||LVCMOS33||Ethernet 2 transmit clock input from PHY.|
|M13||14||ETH2_TX_D0||LVCMOS33||Ethernet 2 transmit data 0. Output to Ethernet PHY.|
|14||ETH2_TX_D1||LVCMOS33||Ethernet 2 transmit data 1. Output to Ethernet PHY.|
|M17||14||ETH2_TX_D2||LVCMOS33||Ethernet 2 transmit data 2. Output to Ethernet PHY.|
|L16||14||ETH2_TX_D3||LVCMOS33||Ethernet 2 transmit data 3. Output to Ethernet PHY.|
|N16||14||ETH2_TX_EN||LVCMOS33||Ethernet 2 transmit enable. Output to Ethernet PHY.|
|p15||14||ETH2_RXCLK||LVCMOS33||Ethernet 2 receive clock input from PHY.|
|V17||14||ETH2_RX_D0||LVCMOS33||Ethernet 2 receive data 0. Input from Ethernet PHY.|
|T16||14||ETH2_RX_D1||LVCMOS33||Ethernet 2 receive data 1. Input from Ethernet PHY.|
|U17||14||ETH2_RX_D2||LVCMOS33||Ethernet 2 receive data 2. Input from Ethernet PHY.|
|N17||14||ETH2_RX_D3||LVCMOS33||Ethernet 2 receive data 3. Input from Ethernet PHY.|
|R11||14||ETH2_RX_DV||LVCMOS33||Ethernet 2 receive data valid. Input from Ethernet PHY.|
|U16||14||ETH2_RX_ER||LVCMOS33||Ethernet 2 receive error. Input from Ethernet PHY.|
Ethernet 2 collision detect input from Ethernet PHY.
Ethernet 2 power down or interrupt
Ethernet LED Pin to indicate status. Mode 1: LINK Indication LED; Mode 2: ACT Indication LED
|N14||14||MDC2||LVCMOS33||Ethernet 2 to PHY MII 2 Management clock|
|P18||14||MDIO2||LVCMOS33||PHY MDIO data I/O ( 3-state buffer)|
- Part number: 11AA02E48T-I/TT (Microchip)
- Supply voltage: 3.3V
Pre-programmed Globally Unique, 48-bit Node Address
- Compatible with EUI-48™ and EUI-64™
- 256 x 8 Bit Organization
|FPGA Pin||Bank||I/O Standard||Comment||Function|
|D9||16||LVCMOS33||Serial bit stream (SCIO)||Serial Clock, Data Input/Output|
Storage device name
|SPI Flash OTP Area||Empty, not programmed||Except serial number programmed by flash vendor|
|SPI Flash Quad Enable bit||Programmed||Must be programmed for SPI Flash Boot|
|SPI Flash main array||demo design|
|EFUSE USER||Not programmed|
|EFUSE Security||Not programmed|
Current Hardware Revision
Vin supply voltage
Vin33 supply voltage
I/O voltage on any FPGA I/O
Voltage on JTAG pins
When Vin33 is powered
|Vin supply voltage||2.4||5.5||V|
|Vin33 supply voltage||1||3.465||V|
|PL IO Bank supply voltage for HR I/O banks (VCCO)||1.14||3.465||V||Xilinx document DS181|
|I/O input voltage for HR I/O banks||-0.20||Vcco+0.20||V||Xilinx document DS181|
|Voltage on Module JTAG pins||3.135||3.465||V||Xilinx document DS181|
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thikness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
Download physical dimensions here: TE0710 Physical Dimensions
3.3 V to 5.5 V
Typical 200mA, depending on customer design and connections.
Vin 3.3 V
Typical 50mA, depending on customer design and connections.
For startup, a power supply with minimum current capability of 2A is recommended.
Vin and Vin 3.3V can be connected to the same source (3.3 V).
Commercial grade modules
0 °C to +70 °C
Industrial grade modules
-40 °C to +85 °C
Depending on the customer design, additional cooling might be required.
Recommended Software: Xilinx Vivado WebPACK (free license)
A15T, A35T, A50T, A75T are not supported by Xilinx legacy tools (ISE, Impact).
The schematic is available for download here:
Document Change History
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