Table of Contents
Trenz Electronic TE0710 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, Dual 10/100 MBit Ethernet PHYs, 512 MByte DDR3 SDRAM with 8-bit data-width, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips. All modules in 4 x 5 cm form factor are mechanically compatible.
All this on a tiny footprint, smaller than a credit card, at the most competitive price.
Figure 1: TE0710-02 Block Diagram
Figure 2: TE0710 (REV 02).
- Artix-7 (15T to 100T) FPGA
- TPS51206 DDR3-SDRAM voltage supply
- MEM4G08D3EABG 512 MByte DDR3 SDRAM
- EN5311QI Voltage Regulator 1.5V
- S25FL256S 32 Mbyte Quad SPI Flash memory
- System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
- EN6347QI voltage Regulator 1.0V
- SiT8008AI 25 MHz Ethernet reference clock
- B2B connector JM2 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM1 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- EN5311QI voltage Regulator 1.8V
- SiT8008AI 100 MHz reference clock (connected to FPGA bank 35)
Industrial-grade Xilinx Artix-7 (15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool
Rugged for shock and high vibration
512 MByte DDR3 SDRAM
Dual 10/100 MBit Ethernet PHY
MAC Address EEPROM
32 MByte QSPI Flash memory (with XiP support)
100 MHz MEMS oscillator
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
112 FPGA I/Os (51 differential pairs) are available on board-to-board connectors
On-board high-efficiency DC-DC converters
4.0 A x 1.0 V power rail
1.0 A x 1.8 V power rail
1.0 A x 1.5 V power rail
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
Evenly-spread supply pins for good signal integrity
Assembly options for cost or performance optimization available upon request.
Initial Delivery State
|Storage device name|
SPI Flash OTP Area
Empty, not programmed
Except serial number programmed by flash vendor.
SPI Flash Quad Enable bit
SPI Flash main array
Table 1: Initial delivery state
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the FPGA's I/O banks and B2B connector:
|Bank||Type||B2B Connector||I/O Signal Count||Voltage||Notes|
HR-Banks support voltages from 1.2V to 3.3V standards.
See the Artix-7 datasheet (DS181) for the allowable voltage range.
24 LVDS-pairs possible
3 LVDS-pairs possible
24 LVDS-pairs possible
|35||HR||-||-||1.5V||connected to 512 MByte DDR3 SDRAM|
Table 2: Voltage ranges and pin-outs of available logic banks of the FPGA
Please use Master Pinout Table table as primary reference for the pin mapping information.
JTAG access to the Xilinx Artix-7 and to the System Controller CPLD is provided through B2B connector JM2.
|JTAG Signal||B2B Connector|
Table 3: Pin-mapping of JTAG Interface on B2B connector
Select by JTAGEN pin on B2B connector JM1-89 either to access FPGA Artix-7 (JTAGEN pin driven low or open) or System Controller via JTAG (JTAGEN pin driven high).
The use of Xilinx legacy development tools (ISE, Impact) is not recommended. Impact recognizes only A100T, any smaller Artix-7 FPGA is not recognized as Xilinx FPGA by Impact.
System Controller I/O Pins
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
|Pin Name||Mode||Function||Default Configuration||B2B Connector|
|PGOOD||Output||Power Good||Active high when all on-module power supplies are working properly.||JM1-30|
|RESIN||Input||Reset||Active low reset signal, drive low to keep the system in reset (FPGA pin PROG_B will be driven by CPLD)||JM2-18|
|JTAGEN||Input||JTAG Select||Low for normal operation, high (3.3V) to programm the System Controller CPLD||JM1-89|
Table 4: Pin-description of System Controller CPLD
On the SoM TE0710 there is a total of 3 LEDS available. Two LEDs are status LEDs, one can freely used in costumer designs. The user LED is routed to the FPGA by the net with the schematic-name 'USERLED'.
When the FPGA is not configured the status LEDs will flash continuously. Finally once FPGA configuration has completed the status LEDs can be used in the user's FPGA design.
|LED||Color||Connected to pin||Description and Notes|
|D1||red||SYSLED2||System Controller status LED, connected to CPLD|
|D2||green||SYSLED1||System Controller status LED, connected to CPLD|
|D3||red||USERLED||User LED, active LOW, connected to FPGA Pin L15|
Table 5: Description of the on board LEDs
The TE0710 is equipped with two Sitara reference clocks to provide clock signals to the Ethernet PHYs and for the on board 512 MByte DDR3 SRRAM.
|U9 SiT8008AI-73-XXS-25.000000E||ICs U3, U6 TLK106RHB||clock signal shared by both Ethernet PHYs|
|DDR3 SDRAM reference||100 MHz|
|FPGA bank 35, pin F4||forwarded as differential clock signal to DDR3 SDRAM IC U12 MEM4G08D3EABG-125|
Table 6: Clocks overview
32 Mbyte Quad SPI Flash Memory
An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data rate will be dependent on the bus width and clock frequency.
SPI Flash QE (Quad Enable) bit must be set, or the FPGA would not configure from Flash. This bit is always set at manufacturing.
The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Low level at RESIN pin also resets the FPGA. This signal can be driven from the user’s PCB via the B2B connector pin JM2-18. Input EN1 is also gated to FPGA Reset, should be open or pulled up for normal operation. EN1 low does not turn off on board DCDC converters.
It is possible for the user to create their own system controller design using the Lattice Diamond software. Once created the design can be programmed into the device using the JTAG pins. The signal JTAGEN should be set to 3.3V to enable programming mode. For normal operation it should be set to 0V.
There are two LEDs that are connected to the system controller. When the FPGA is not configured the LEDs will flash continuously. Finally once FPGA configuration has completed the LEDs can be used in the user's FPGA design.
The TE0710-02 board is equipped with one DDR3 SRRAM IC (U12) with a capacity of 512 MByte volatile memory for storing user code and data.
- Part number: MEM4G08D3EABG-125 (Memphis)
- Supply voltage: 1.5V
- Organization: 64M words x 8 bits x 8 banks
- Memory speed limited by Artix speed grade and MIG
Configuration of the DDR3 memory controller in the FPGA should be done using the Xilinx MIG tool in the Vivado IP catalog.
The TE0710-02 is equipped with two The I/O Voltage is fixed at 3.3V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U9). 10/100 MBit Ethernet PHYs (U3 and U6).
Both Ethernet PHYs are connected to FPGA Bank 14 using MII interface.
Note: Pin ETH2_INT (power down or interrupt, default function is power down) is connected to FPGA bank 16 (pin D10).
Power and Power-On Sequence
Power supply with minimum current capability of 2A for system startup is recommended.
|Power Input Pin||Voltage Range||Max Current|
|VIN||3.3V to 5.5V||Typical 200mA, depending on customer design and connections.|
|3.3VIN||3.3V||Typical 50mA, depending on customer design and connections.|
Table 7: maximal current of power supplies
Vin and Vin 3.3V can be connected to the same source (3.3 V).
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS181 (for Artix7) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0710 module.
A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stable. Than 3.3V supply will be available on the B2B connector pins.
The regulators can be powered from the 3.3V supply or a 5V supply if preferred. The options for powering the board are as follows:
- Apply 5V to pins VIN and 3.3V to pins 3.3VIN on the board connector
- Apply 3.3V to pins VIN and 3.3VIN on the board connectors.
Voltages on B2B-
|B2B JM1-Pin||B2B JM2-Pin||Direction||Note|
1, 3, 5
|2, 4, 6, 8||input||supply voltage|
|3.3VIN||13, 15||-||input||supply voltage|
|VCCIO15||9, 11||-||input||high range bank voltage|
|VCCIO34||-||7, 9||input||high range bank voltage|
|3.3V||14||10, 12, 91||output||internal 3.3V voltage level|
|1.8V||39||-||output||internal 1.8V voltage level|
|1.5V||-||19||output||internal 1.5V voltage level|
Table 8: Power rails of SoM on B2B connectors
|15||VCCIO15||user||HR: 1.2V to 3.3V|
|34||VCCIO34||user||HR: 1.2V to 3.3V|
Table 9: Range of FPGA's bank voltages
See the Artix7 datasheet DS181 for the allowable voltage range.
Board to Board Connectors
Variants Currently In Production
FPGA Junction Temperature
|Operating Temperature Range|
|TE0710-02-100-2CF||XC7A100T-2CSG324C||0°C to 85°C||commercial grade|
|TE0710-02-35-2CF||XC7A35T-2CSG324C||0°C to 85°C||commercial grade|
|TE0710-02-100-2IF||XC7A100T-2CSG324I||-40°C to 100°C||industrial grade|
|TE0710-02-35-2IF||XC7A35T-2CSG324I||-40°C to 100°C||industrial grade|
|TE0710-02-100-1Q||XA7A100T-1CSG324Q||-40°C to 125°C||industrial grade|
Table 10: Differences between variants of Module TE0710-02
Absolute Maximum Ratings
VIN supply voltage
|-0.3||7.0||V||EN6347QI / EN5311QI data sheet|
|3.3VIN supply voltage|
|PL IO bank supply voltage for HR I/O Banks (VCCO)||-0.5||3.6||V||-|
|I/O input voltage for HR I/O banks||-0.4||VCCO_X+0.55||V||-|
|Voltage on module JTAG pins|
|VCCO_0+0.45||V||VCCO_0 is 3.3V nominal.|
Table 11: Absolute maximum ratings
Recommended Operation Conditions
|VIN supply voltage||2.4||5.5||V||-||EN5311QI data sheet|
|3.3VIN supply voltage||3.135||3.465||V||-|
3,3V ± 5%
| PL I/O bank supply voltage for HR|
I/O banks (VCCO)
Xilinx datasheet DS181
|I/O input voltage for HR I/O Banks||- 0.20||VCCO + 0.2||V||-|
Xilinx datasheet DS181
|Voltage on Module JTAG pins||3.135||3.465||V||-||3,3V ± 5%|
Table 12: Recommended operation conditions
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: 8mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers.
All dimensions are shown in mm.
Figure 3: Physical Dimensions of the TE0710-02 board
|11.5 g||without bolts|
|20.3 g||with bolts|
Hardware Revision History
|02||Current Hardware Revision|
|01||First production release|
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
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