Skip to end of metadata
Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 17 Next »

 

 

TypeFile PrefixFile ExtentionExampleDescription
Altium 3D export3D*-.pdf3DT-TE0722-01.PDFStatic Altium 3D export of the PCB
Altium 3D PDFPDF3D-.pdfPDF3D-TEB0745-02.PDFInteractive 3D PDF of the PCB
Altium ProjectAP-.zip Complete Altium CAD  Project for reference
Altium LibAL-.zip Altium Library Files (.lib) compressed as ZIP-file
Application Note(s)AN-   
Assembly Diagram AD-.pdf AD-TE0715-02.pdf Assembly Diagrams with board dimension and connector position as pdf
Bill of MaterialsBOM-.csv, .pdf, .xlsx, .ods  
Block Diagram SVGBD-.svgBD-TE0841-01.svgInkscape SVG file (for TE internal use only)
Block Diagram PNGBD-.pngBD-TE0841-01.pngInkscape SVG export for TRMs, web, etc.
Cooler-STEP STP- .zip (.step),.pdf STP-26923-TE0715-Heatsink.zip,26923-TE0715-Heatsink.pdf Cooler 3D STEP (ISO 10303) model (.step) compressed as ZIP-file or pdf document
EDA library (file(s))*---.LIB-xxx.zip (.lib) TE0720 GigaZee JBx.LIB-Altium.zip Altium/Eagle Library Files (.lib) compressed as ZIP-file
EDA project (file(s))*---.PRJ-xxx.zipTE0xxx-xx.PRJ-Altium.zipAltium/Eagle Project Files
Electronic Design Interchange FormatEDIF-.zip (.edf)

EDIF-TE0600-03.zip

Altium EDIF export of the PCB
EU declaration of conformityDoC-   
Gerber FilesGB-.zip  Manufacturing files (Gerber files and numerical control drill files) compressed as ZIP-file
Operating InstructionsOI-   
Product BriefPB-   
PCB-STEPSTP-.zip (.step)STP-TE0715-02.zip PCB 3D STEP (ISO 10303) model compressed as ZIP-file
PCN PCN-.pdfPCN-20160114 TE0720-02 to TE0720-03, CPLD upgrade to REV05-v1-20160122_0830.pdfProduct change notifications
Pick and PlacePP-   
Schematics SCH-.pdf SCH-TE0726-02M.PDF PCB Schematic as pdf
System Controller* ---.JEDSC0720_04_1AF.JED Firmware for PCB-CPLDs (Lattice FPGA). Free Programmer Software available on Lattice Semiconductor.
System Controller FileSC-PGM-.zip (.jed)SC-PGM-TE790-02_STDRXTXSWAP-01_20160308.zipSystem Controller Programming File. JED files are firmware for PCB-CPLDs (Lattice FPGA). Free Programmer Software available on Lattice Semiconductor.
System Controller SourceSC-PRJ-.zipSC-PRJ-TE790-02_STDRXTXSWAP-01_20160308.zipSystem Controller Source Code and Project files for PCB-CPLDs (Lattice FPGA). Free Development Software available on Lattice Semiconductor.
Trace LengthTL-.csv, .pdf, .xlsx, .xls, .ods, .zip 

PCB Trace Length

Technical Reference ManualTRM-.pdfTRM-TE0715-03.pdf 
Vivado Design---.zipte0720-test_board-vivado_2016.2-build_03_20160630150948.zipZIP files with FPGA Reference Design as TCL script with Batch-Files to create the Vivado project.
Design- and Programmer Software available on Xilinx.
Attention: Only Programmer (LabTools) is freeware, but depending on FPGA, the Design-Software is not always free.
Vivado SDSoC---_sdsoc.zip.zip

 

te0726_m_sdsoc.zip

SDSOC ready Platform Project

* old style, only for some older documents

Documents Naming Conventions

 

 

  • No labels