Project Delivery

Quick Start

The most Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

The "normal" Vivado project will be generated in the subfolder "/vivado/" after executing scripts (YouTube: TE0720 Project Creation).

There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects.

If you use our prepared batch files for project creation do the following steps:

1. open "design_basic_settings.cmd/.sh" with text editor and set correct vivado path and board part number. How select the correct board part number is described on TE Board Part Files
2. run "vivado_create_project_guimode.cmd/.sh"

See  Reference Design: Getting Started for more details.

If you need our Board Part files only, see Board Part Installation.

Zip Project Delivery

Zip Name Description

Last supported Release

Currently limitations of functionality

• • Important Note: QSPI Programming need special FSBL on 2017.4 for all Zynq/ZynqMP. Special programming FSBL will be provided on 2017.4 reference designs
  • Linux OS only: HSI software generation failed.
    • Reason: start "gmake" failed, alias is not set on Ubuntu
    • Workaround: "sudo ln -s /usr/bin/make /usr/bin/gmake" to generate alias or use  SDK GUI to generate applications and boot files.
  • Linux OS only: Function, which used external programs.
    • Reason: Currently only set correctly for Win OS.
    • Workaround: Change TCL scripts program path manually.

Directory structure

Command Files

Command files will be generated with "_create_win_setup.cmd" on Windows  and "_create_linux_setup.sh" on Linux OS. Linux shell files are currently not available for this release.

Windows Command Files

Linux Command Files

TE-TCL-Extentsions

Design Environment: Usage

Reference-Design: Getting Started

• Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
  (optional) Install Xilinx Vivado LabTools (Lab Edition)
• Configure the reference-design:
  1. Open “design_basic_settings.cmd” with a text-editor:
      a. Set correct Xilinx Environment:
          @set XILDIR=C:/Xilinx
          @set VIVADO_VERSION=2017.4
          Program settings will be search in :
          %XILDIR%/VIVADO/%VIVADO_VERSION%/
          %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
          %XILDIR%/SDK/%VIVADO_VERSION%/
          Example directory: c:/Xilinx/Vivado/2017.4/
          Attention: Scripts are supported only with predefined Vivado Version!
      b. Set the correct module part-number:
          @set PARTNUMBER=x
          You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
      c. Set Application name (for programming with batch-files only):
          @set SWAPP=NA
          NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
         <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
• Create all prebuilt files in one step:
  2. Run “design_run_project_batchmode.cmd”
• (optional to Step 2) Create all prebuilt files in single steps:
  3. Run “vivado_create_project_guimode.cmd”:
      A Vivado Project will be create and open  in ./vivado
  4. Type “TE::hw_build_design” on Vivado TCL-Console:
      Run Synthese, Implement and create Bitfile and optional MCSfile
  5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
      Create all Software Applications from <design_name>/sw_lib/apps_list.csv
  6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
      Create a SDK Project in <design_name>/workspace/sdk
      Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps

• Programming FPGA or Flash Memory with prebuilt Files:
  7. Connect your Hardware-Modul with PC via JTAG.
  With Batch-file:
  8. (optional) Zynq-Devices Flash Programming (*.bin):
      Run “program_flash_binfile.cmd”
  9. (optional) FPGA-Device Flash Programming (*.mcs):
      Run “program_flash_mcsfile.cmd”
  10. (optional) FPGA-Device Programming (*.bit):
        Run “program_fpga_bitfile.cmd”
  With Vivado/Labtools TCL-Console:
  11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado  or LabTools
  12. (optional) Zynq-Devices Flash Programming (*.bin):
        Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
        Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  13. (optional) FPGA-Device Flash Programming (*.mcs):
        Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
        Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  14. (optional) FPGA-Device Programming (*.bit):
        Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
        Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

Basic Design Settings

Project Configuration

1. Unzip project files
2. Rename basefolder (basefolder name is used as project name)
3. Edit design_basic_settings.cmd
   1. Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
   2. Select the correct board part number for your PCB  (See: Windows Command Files → design_basic_settings.cmd)
   3. Other settings are optional  (See: Windows Command Files → design_basic_settings.cmd)
4. Excecute vivado_create_project_guimode.cmd or vivado_create_project_batchmode.cmd to generate a vivado project with the predefined Block Design from the Block Design folder
5. Open Vivado with vivado_open_existing_project_guimode.cmd (if you use vivado_create_project_guimode.cmd on step 4, you didn't need this)
6. Open the Block Design and create your own design inside this Block Design.
7. Backup your Block Design as tcl-script: Type "TE::hw_blockdesign_export_tcl" on Vivado Tcl Console. The old one will be overwritten.
8. Build your Design...

Initialise TE-scripts on Vivado/LabTools

• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      
      • for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
      • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
        
    • Press Enter
    • A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source ../scripts/reinitialise_all.tcl
      

Use predefined TE-Script functions

• Variant 1 (recommended):
  • Typ function on Vivado TCL Console, ex.: TE::help
  • TE::help
    
    • Show all predefined TE-Script functions.
  • TE:<functionname> -help 
    
    • Show short description of this function.
    • Attention: If -help argument is set, all other args will be ignored. 
• Variant 2:
  • Create your own function Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push +
    • Type Name ex.: Run SDK
      
    • Press Enter
      
    • Select Run command and insert function:
      • Variante 1 (no Vivado request window for args):
        • insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
      • Variant 2 (Vivado request window for args):
        • insert function, ex.:TE::sw_program_zynq
        • Press Define Args...
        • For every arg:
          
          • Push
          • Typ Name, Comment, Default Value and set optional
          • Press Enter
            
          • Example for args:
          • • Push
            • Index, Key Name, -swapp,
            • Push
            • Appname, Arg, hello_world,
              
             
    • Press Enter
    • A new Button is shown on the Vivado Gui.

Hardware Design

Board Part Files

See also TE Board Part Files

Structure Board Parts

Board Parts are located on subfolder "board_files", with the name of the special board. Revisions are splitt in the subfolder of the board part <boardpart_name><version>

Every Version of a Board Parts consists of four files:

• board.xml
  
• part0_pins.xml
• preset.xml
• picture.jpg or picture.png

Board Part Carrier Extension

Board Part Carrier Extensions are a TCL-Scripts, which can be sourced in Vivado Block Design. Thy are used with TE-Scripts only. It contains additional settings of PS-System for special carrier-board, if no special Board part file exists.

Board Part Carrier Extensions  are located on subfolder "board_files/carrier_extension/" with file name *_preset.tcl.

Use Reference Designs or Vivado TCL-Console(TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation" 

Board Part CSV Description

Board Part csv file is used for TE-Scripts only.

Block Design Conventions

• Only one Block-Design per project is supported

• Recommended BD-Names (currently importend for some TE-Scripts):
   

  Name	Description
  zsys	Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
  zusys	Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
  msys	Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
  fsys	Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

   
  

• Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help
  

XDC Conventions

• All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
  Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!

• Recommended XDC-Names (used for Vivado XDC-options):

  Property	Name part	Description
  Set Processing Order	*_e_*	set to early
  	*_l_*	set to late
  		set to normal
  Set Used In	*_s_*	used in synthese only
  	*_i_*	used in implement only
  		used in both, synthese and implement

Backup Block Design as TCL-File

• Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
  It will be saved as *_bd.tcl
  Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
                  Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>

Microblaze Firmeware

• Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>.
• For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.

Software Design

HSI: Generate predefined software from libraries

• To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
• All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
• Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app

SDK: Create user software project

• To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
  Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps
• To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type  "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
  
• To open an existing SDK-project without update HDF-Data, type  "TE::sw_run_sdk -open_only" on Vivado-TCL-Console

Advanced Usage

Attention not all features of the TE-Scripts are supported in the advanced usage!

User defined board part csv file

To modifiy current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.

See Chapter Board Part Files for more information.

User defined Settings

Vivado settings:

Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.

Script settings:

Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.

ZIP ignore list:

Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.

SDSOC settings:

SDSOC settings will are deposited on the following folder: "<design_name>/settings/sdsoc"

User defined TCL Script

TCL Files from "<design_name>/settings/usr" will be load automaticaly on script initialisation.

SDSOC-Template

SDSOC description and files to generate SDSoC project are deposited on the following folder: "<design_name>/settings/sdsoc"

HDL-Design

HDL files can be saved in the subfolder "<design_name>/hdl/" or "<design_name>/hdl/<shortname>" and all subfolders of "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.  A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".

To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for synthese only.

RTL-IP-cores (*.xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.

Checklist / Troubleshoot

1. Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
2. Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
3. Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
4. Win OS only: Use short path name, OS allows only 256 characters in normal path.
5. Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be desplay: /bin/sh -> bash. Access rights can be changed with "chmod"
6. Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
7. Did you have the newest reference design build version? Maybe it's only a bug from a older version.
8. Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
9. On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation problem) and the scripts canceled. Please try again. 
   
10. If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ",  the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)

References

1. Vivado Design Suite User Guide - Getting Started  (UG910)
2. Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
3. Vivado Design Suite User Guide - I/O and Clock Planning (UG899)
4. Vivado Design Suite User Guide - Programming and Debugging (UG908)
5. Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
6. SDSoC Environment User Guide - Getting Started (UG1028)
7. SDSoC Environment -  User Guide (UG1027)
8. SDSoC Environment User Guide - Platforms and Libraries (UG1146)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older revision number.

Date	Revision	Vivado Version	Authors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	2017.4	Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]	Work in progress
2017-11-03	v.134	2017.2	John Hartfiel	Last Vivado 2017.2 supported project delivery version
2017-09-12	v.131	2017.1	John Hartfiel	Last Vivado 2017.1 supported project delivery version
2017-04-12	v.126	2016.4	John Hartfiel	Last Vivado 2016.4 supported project delivery version
2017-01-16	v.114	2016.2	John Hartfiel	Last Vivado 2016.2 supported project delivery version
2016-06-21	v.83	2015.4	John Hartfiel	Last Vivado 2015.4 supported project delivery version
2013-03-11	v.1	---	Antti Lukats	Initial release
	All		Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]