Table of contents
Firmware for PCB CPLD with designator U4. CPLD Device in Chain: LCMX02-256HC
- USER IO
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|DONE||in||13||FPGA DONE signal|
|EN_SC3||in||16||B2B Enable Pin|
|F_TCK / C_TCK||out||28||JTAG FPGA|
|F_TDI / C_TDI||out||27||JTAG FPGA|
|F_TDO / C_TDO||in||23||JTAG FPGA|
|F_TMS / C_TMS||out||25||JTAG FPGA|
|JTAGSEL||in||26||Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)|
|MODE_SC1||in||11||B2B Boot Mode Pin|
|NOSEQ_SC4||in||12||B2B NOSEQ Pin / currently_not_used|
|PG_ALL||in||10||Power good from 1.8V Sence on U23|
|PROG_B||out||17||FPGA PROG_B Reset|
|PWR_DIS||out||5||Power disable (U1), Module has external pullup|
|SYSLED1 / LED1||out||9||Green LED D4|
|TCK_SC7 / M_TCK||in||30||JTAG B2B|
|TDI_SC6 / M_TDI||in||32||JTAG B2B|
|TDO_SC5 / M_TDO||out||1||JTAG B2B|
|TMS_SC8 / M_TMS||in||29||JTAG B2B|
|UFL||out||4||J1 (Ultra Small Sufrace Mount Coax)|
|UI_CLK / XB_SC||out||20||FPGA Bank 16 Pin B8|
|UIO / XA_SC||in||21||FPGA Bank 16 Pin D10|
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
PROG_B is nRST_SC0 and PG_ALL and EN_SC3 after power on delay.
Power Good (STAT_SC2) is PGALL and EN_SC3.
PWR_DIS is high impedance.
MODE_SC1 is connected to XBSC.
XA_SC is connected to UFL.
Green LED D4
|On||Done is low, FPGA not programmed|
|OFF||Done is high, FPGA is programmed|
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|REV01||REV01||REV01 , Firmware released 2015-04-17|
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