TE0782 TRM

Overview

The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC (XC7Z035, XC7Z045 or XC7Z100).

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

Key Features

• Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoC
• Rugged for shock and high vibration
• Large number of configurable I/Os are provided via rugged high-speed stacking strips
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2.0 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• 2 x MAC-address EEPROMs
• Optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte) or optional 2 x 64 MByte HyperFLASH
• Temperature compensated RTC (real-time clock)
• Si5338 PLL for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

Assembly options for cost or performance optimization available upon request.

Block Diagram

Main Components

1. Xilinx Zynq XC7Z SoC (XCZ035, XC7Z045 or XC7Z100), U1
2. Lattice Semiconductor MachXO2 1200HC System Controller CPLD, U14
3. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U19
4. Intelligent Memory 4Gbit DDR3L-1600 SDRAM, U10
5. Spansion 32 MByte QSPI Flash memory, U38
6. SI5338A PLL programmable clock generator, U2
7. TI low-dropout linear regulator @1.5V, U23
8. Microchip USB3320C USB PHY transceiver, U8
9. Microchip USB3320C USB PHY transceiver, U4

10. Intersil ISL12020MIRZ Real Time Clock, U17

11. LT quad 4A PowerSoC DC-DC converter (1.0V), U13

12. LT quad 4A PowerSoC DC-DC converter (3.3V, 1,8V, 1.2V_MGT, 1.0V_MGT), U16

13. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
14. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
15. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3

16. Micron Technology 4 GByte eMMC, U15

17. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
    
18. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
    

Initial Delivery state

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoC's I/O banks and B2B connector:

For detailed information about the pin out, please refer to the Master pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq device is provided through B2B connector J3.

JTAG access to the System Controller CPLD device is provided through B2B connector J3.

System Controller CPLD I/O Pins

Special purpose pins to configure and operate the System Controller CPLD (IC U14):

Some of the functions of the SoM are controlled by the System Controller CPLD and it's firmware. User can change this by using(creating) different firmware for the System Controller CPLD.

On-board LEDs

Clocking

Silicon Labs PLL Si5338 is used to supply reference clock for MGT banks. Optionally MGT reference clocks can also be supplied from the baseboard for any of the MGT banks. Reference clock for the Si5338 quad clock generator itself can be supplied by the on-board oscillator (U3) or from the baseboard.

Default MIO Mapping

Gigabit Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11).

ETH1 PHY connection:

ETH2 PHY connection:

USB Interface

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).  

USB0 PHY connection:

USB1 PHY connection:

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I²C addresses for on-board components:

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are useable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board peripherals

Processing System (PS) Peripherals

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U17). Battery voltage must be supplied to the module from the baseboard. Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

PLL - Phase Locked Loop

The TE0782 is also equipped with a Silicon Labs programmable clock quad generator Si5338A (U2). The Si5338 is accessible for programming over I²C bus at slave address 0x70.

MAC-Address EEPROM's

Two Microchip 24AA025E48 serial EEPROM's (U22 and U24) are used for storing globally unique 48-bit node addresses,  are compatible with EUI-48(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. EEPROM's are accessible through I²C nus at slave address 0x50 for MAC-Address1 (U22), 0x51 for MAC-Address2 (U24) .

Boot Process

TE0782's primary boot device is on-board SPI Flash. Boot from on-board eMMC is also supported (FSBL must be loaded from SPI Flash).

JTAG boot mode option is always available.

Power and Power-On Sequence

Input Power Supply

Bank Voltages

Power-up sequence at start-up

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Voltage levels of the I/O signals must not get higher than VCCIO + 0.4V.

Board to Board Connectors

The TE0782 module has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

Technical Specification

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Industrial grade: -40°C to +85°C.

Module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Please download the assembly diagram for exact values.

• Module size: 85 mm × 85 mm.

• Mating height with standard connectors: 5 mm

• PCB thickness: 1,7 mm

All dimensions are shown in millimeters.

Weight

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

Date	Revision	Contributors	Description
2018-01-31		Ali Naseri	updated Power section, added diagramms
2017-06-07	v19	Jan Kumann	Minor formatting
2017-05-23	V13	Jan Kumann	New block diagram. New product images. New physical dimensions drawing.
2017-01-24	V12	Ali Naseri	New numbered pictures describing main components. Added variants in production.
2016-06-27	v10	Ali Naseri, Jan Kumann	Initial release.

Disclaimer