Table of contents
Firmware for PCB CPLD with designator U18. CPLD Device in Chain: LCMX02-256HC
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|CPLD_IO / XIO||in||17||FPGA Bank 45 P28|
|DONE||in||13||FPGA Configuration DONE_0 Pin|
|EN_PL||20||(currently internal DCDC Pullup is used to enable power) / currently_not_used|
|F_TCK / C_TCK||out||8||JTAG to FPGA|
|F_TDI / C_TDI||out||10||JTAG to FPGA|
|F_TDO / C_TDO||in||11||JTAG to FPGA|
|F_TMS / C_TMS||out||9||JTAG to FPGA|
|INIT_B||in||16||FPGA INIT_B / currently_not_used|
|JTAGMODE||in||26||Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to FPGA, one: CPLD access)|
|/ LED1||out||4||green LED D1|
|N.C. / dummy||out||5||dummy pin|
|nRST_SC0 / RESIN||in||21||B2B Reset_N|
|PROG_B||out||12||FPGA Configuration PROGRAM_B_0 Pin|
|SC1||23||B2B JM1-32 / currently_not_used|
|SC2||25||B2B JM1-30 / currently_not_used|
|SC3||27||B2B JM1-28 / currently_not_used|
|SC4||28||B2B JM1-7 / currently_not_used|
|TCK / M_TCK||in||30||JTAG from B2B connector|
|TDI / M_TDI||in||32||JTAG from B2B connector|
|TDO / M_TDO||out||1||JTAG from B2B connector|
|TMS / M_TMS||in||29||JTAG from B2B connector|
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).
RESIN is connected to PROG_B.
PUD_C is set to zero.
Green LED D1.
|ON||1||B2B Reset is set|
|Blinking||2||Done is low (FPGA not programmed)|
|User Defined||3||XIO is connected to LED|
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|REV01||REV01||REV01 , Firmware released 2016-11-02|
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