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Table of Contents
Overview
The Trenz Electronic TEI0010 AnalogMax is a low cost small-sized FPGA module integrating an Intel MAX 10 FPGA SoC, 8 MByte serial memory for configuration and operation and 8 MByte SDRAM. The board is equipped with several sensors for analog values like a 3-axis accelerometer, temperature sensor, smoke detector and a 8-channel 12bit ADC/DAC.
Refer to http://trenz.org/analogmax-info for the current online version of this manual and other available documentation.
Key Features
Intel MAX 10 10M08 FPGA SoC
- 8 MByte SDRAM
8 MByte QSPI Flash memory
- Onboard oscillator with 3 selectable frequencies
- Analog Devices ADXL362BCCZ MEMS 3-axis accelerometer
- Analog Devices ADT7320UCPZ temperature sensor
- Analog Devices ADPD188BI smoke detector
- Analog Devices AD5592RBCPZ ADC/DAC
- JTAG and UART over Micro USB2 connector
- 1x6 pin header for JTAG access to FPGA SoC
- 1x PMOD header providing 8 GPIOs
2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs with 7 analog inputs as alternative function
- 1x 3-pin header providing 2 analog inputs or 1 GPIO
8x user LEDs
- 1x user push button
- 5.0V single power supply with on-board voltage regulators
- Size: 61.5 x 25 mm
Block Diagram
Figure 1: TEI0010 block diagram
Main Components
Figure 2: TEI0010 main components
- Intel MAX 10 10M08 FPGA SoC, U1
- 8 Mbyte SDRAM 166MHz, U2
- LT LTC1799 oscillator, U10
- Analog Devices ADXL362BCCZ MEMS 3-axis accelerometer, U11
- Analog Devices ADT7320UCPZ temperature sensor, U8
- Analog Devices ADPD188BI smoke detector, U14
- Winbond W74M64FV QSPI Flash memory, U5
- Analog Devices AD5592RBCPZ ADC/DAC, U12
- 12.0000 MHz MEMS oscillator, U7
- FTDI USB2 to JTAG/UART adapter, U3
- Push button (reset), S1
- Micro USB2 B socket (receptacle), J9
- Configuration EEPROM for FTDI chip, U9
- Push button (user), S2
- 8x red user LEDs, D2 ... D9
- Red LED (Conf. DONE), D10
- Green LED (indicating 3.3V supply voltage), D1
- 3-pin header (2.54mm pitch), J3
- 1x14 pin header (2.54mm pitch), J1
- 1x6 pin header (2.54mm pitch), J4
- 1x14 pin header (2.54mm pitch), J2
- 2x6 Pmod connector, J6
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
| Quad SPI Flash, U5 | DEMO Design | - |
| FTDI chip configuration EEPROM, U9 | Programmed | - |
Table 1: Initial delivery state of programmable devices on the module.
Control Signals
To get started with TEI0010 board, some basic signals are essential and are described in the following table:
Control signal | Switch / Button / LED / Pin | Signal Schematic Names | Connected to | Functionality | Notes |
|---|---|---|---|---|---|
| MAX10 FPGA U1 JTAGEN | header J4, pin 2 | JTAGEN | MAX10 FPGA U1, bank 1B, pin E5 | high: MAX 10 JTAG enabled, floating: MAX 10 JTAG disabled | switch the JTAG pins to user GPIO's if drive this pin to GND |
| MAX10 FPGA U1 Reset | header J2, pin 10 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active reset line | also connected to Reset push button S1 |
| Supply voltage indicator | Green LED D1 | 3.3V | DCDC U4 | indicating 3.3V voltage level | - |
| Configuration DONE indicator | Red LED D10 | CONF_DONE | MAX10 FPGA U1, bank 8, pin C5 | indicating FPGA configuration completed | ON: configuration completed, OFF: FPGA not configured |
| Reset Push button | S1 | RESET | MAX10 FPGA U1, bank 8, pin E7 | low active logic | - |
| User Push button | S2 | USER_BTN | MAX10 FPGA U1, bank 8, pin E6 | low active logic | available to user |
Table 2: TEC0850 Control Signals
Boot Process
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:
| Bank | Connector Designator | I/O Signal Count | Bank Voltage | Notes |
|---|---|---|---|---|
| 2 | J1 | 4 I/O's | 3.3V | - |
| J6 | 8 I/O's | Pmod connector | ||
| 5 | J1 | 2 I/O's | 3.3V | - |
| J2 | 9 I/O's | 2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors) | ||
| 1B | J4 | JTAG interface and 'JTAGEN' signal (5 I/O's) | 3.3V | JTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions |
| J3 | 1 I/O | - |
General overview of single ended I/O's
FPGA I/O banks
Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:
| Bank | I/O's Count | Connected to | Notes |
|---|---|---|---|
| 2 | 4 | 1x14 pin header, J1 | user GPIO's |
| 8 | Pmod connector, J6 | user GPIO's | |
| 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | |
| 1 | reference clock oscillator, U10 | reference clock input from oscillator U10 | |
| 1 | accelerometer IC, U11 | interrupt 1 line of Analog Devices MEMS accelerometer | |
| 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6 |
| 1 | accelerometer IC, U11 | interrupt 2 line of Analog Devices MEMS accelerometer | |
| 1 | reference clock oscillator, U10 | oscillator adjustable with three steps of clock output | |
| 1 | temperature sensor IC, U8 | interrupt line of temperature thresholds | |
| 6 | 18 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 3 | 22 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 3 | SPI interface connected to IC U8, U11, U12 | SPI interface (MISO, MOSI, MCLK) for temperature sensor U8, 3-axis accelerometer U11 and ADC/DAC U12 | |
| 1 | temperature sensor IC, U8 | chip-select line for SPI interface | |
| 1 | accelerometer IC, U11 | chip-select line for SPI interface | |
| 1 | ADC/DAC IC , U12 | Synchronization line of ACD/DAC IC (active low control input) | |
| 1 | temperature sensor IC, U8 | interrupt line of critical temperature | |
| 1A | 8 | 1x14 pin headers J1 | 7 analog inputs or GPIO's, 1 pin analog reference voltage input |
| 2 | pin headers J1 | 1 analog inputs or GPIO, 1 dedicated analog input | |
| 1B | 5 | pin header J4 | 4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND |
| 8 | 8 | LEDs D2 ... D9 | Red user LEDs |
| 6 | QSPI Flash memory, U5 | 6 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization | |
| 6 | FTDI FT2232H JTAG/UART adapter, U3 | 6 pins configurable as GPIO/UART or other serial interfaces | |
| 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | |
| 1 | User button S2 | user configurable | |
| 1 | Reset button S1 and pin J2-10 | low active reset line for FPGA reconfiguration |
General overview of single ended I/O's
On-board Peripherals
Subsections...
Power and Power-On Sequence
Power Consumption
Power Distribution Dependencies
Figure x: Power Distribution
Power-On Sequence
Create DrawIO object here: Attention if you copy from other page, objects are only linked.
Figure x: Power Sequency
Voltage Monitor Circuit
Power Rails
Bank Voltages
Board to Board Connectors
Technical Specifications
Absolute Maximum Ratings
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
Table x: Module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
Table x: Recommended Operating Conditions.
Physical Dimensions
Figure x: Physical dimensions drawing
Variants Currently In Production
| Trenz shop TE0xxx overview page | |
|---|---|
| English page | German page |
Table x: Trenz Electronic Shop Overview
Revision History
Hardware Revision History
| Date | Revision | Note | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 | Prototypes | - | - |
Table x: Module absolute maximum ratings.
Document Change History
| Date | Revision | Contributor | Description |
|---|---|---|---|
|
Table x: Document change history.
Disclaimer
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
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REACH, RoHS and WEEE
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Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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