Table of Contents
The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
Intel® MAX 10 Commercial [10M08SAU169C8G]
Speed Grade: C8 (Slowest)
Temperature: 0°C ~ 85°C
Package compatible device 10M02...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
Dimension: 86.5mm x 25mm
SMA Connector, J5...6
Amplifier, U12- U14- U6
Series Voltage Reference, U8
Analog to Digital Convertor, U15
Voltage Regulator, U10- U13- U16
Switching Voltage Regulator, U11- U4
Intel® MAX 10, U1
SDRAM Memory, U2
Active serial Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
4Kb EEPROM, U9
Configuration LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB2 Receptacle, J9
1x14 pin header (Not assembled), J2
1x6 pin header (Not assembled), J4
1x14 pin header (Not assembled), J1
Initial Delivery State
Storage device name
Quad SPI Flash
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
|Push Button||Pin Header||Note|
|S1||J2||connected to nCONFIG|
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
|FPGA Bank||Connector Designator||I/O Signal Count||Voltage Level||Notes|
|Bank 1B||J4||5||3.3V||JTAG interface|
FPGA I/O Banks
|FPGA Bank||I/O Signal Count||Connected to||Notes|
|Bank 1A||7||1x14 Pin header, J1||AIN0...6|
|Bank 1B||5||1x6 Pin header, J4||JTAG_EN, TDI, TDO, TMS, TCK|
|Bank 2||4||1x14 Pin header, J1||D2...5|
|5||A2D, U15||ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV|
|1||12MHz Oscillator, U7||CLK12M|
|2||Amplifier, U12||nIAMP_A0, nIAMP_A1|
|Bank 3||22||SDRAM, U2||RAM_ADDR_CMD|
1x14 Pin header, J2
|2||1x14 Pin header, J1||DIO0...1|
|Bank 6||16||SDRAM, U2||DQ0...15|
|Bank 8||8||User Red LEDs, D2...9||LED0...7|
|6||SPI Flash, U5||F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn|
|1||Red LED, D10||CONF_DONE|
|6||FTDI JTAG/UART Adapter, U3||BDBUS0...5|
|1||Push Button, S2||USER_BTN|
Micro USB2.0 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
|VBUS||USB_VBUS||It is connected to GND|
FTDI FT2232H U3,
FTDI FT2232H U3,
JTAG access to the TEI0015 SoM through pin header connector J4.
Pin Header Connector
|JTAG_EN||J4-2||Connected to 3.3V|
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
|SDRAM I/O Signals|
Signal Schematic Name
A0 ... A13
|Bank address inputs|
BA0 / BA1
DQ0 ... DQ15
DQM0 ... DQM1
Row Address Strobe
Column Address Strobe
|WE||bank 3||Write Enable|
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
|FTDI Chip U3 Pin||Signal Schematic Name||Connected to||Notes|
|ADBUS0||TCK||FPGA bank 1B, pin G2||JTAG interface|
|ADBUS1||TDI||FPGA bank 1B, pin F5|
|ADBUS2||TDO||FPGA bank 1B, pin F6|
FPGA bank 1B, pin G1
|BDBUS0||BDBUS0||FPGA bank 8, pin A4||user configurable|
|BDBUS1||BDBUS1||FPGA bank 8, pin B4||user configurable|
|BDBUS2||BDBUS2||FPGA bank 8, pin B5||user configurable|
|BDBUS3||BDBUS3||FPGA bank 8, pin A6||user configurable|
|BDBUS4||BDBUS4||FPGA bank 8, pin B6||user configurable|
|BDBUS5||BDBUS5||FPGA bank 8, pin A7||user configurable|
Active Serial Configuration
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
|Signal Schematic Name||Connected to||Notes|
|F_CS||FPGA bank 8, pin B3||chip select|
|F_CLK||FPGA bank 8, pin A3||clock|
|F_DI||FPGA bank 8, pin A2||data in / out|
FPGA bank 8, pin C4
|data in / out, configuration dual-purpose pin of FPGA|
|DEVCLRN||FPGA bank 8, pin B9||data in / out, configuration dual-purpose pin of FPGA|
|F_DO||FPGA bank 8, pin B2||data in / out|
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
|FTDI U3, Pin EECS|
|EECLK||FTDI U3, Pin EECLK|
|EEDATA||FTDI U3, Pin EEDATA|
The TEI0015 board is equipped with the 18-bit 2MSPS ADC provided by Analog Devices, .
|Diff Amplifier U14, VOUT-|
|IN-||Diff Amplifier U14, VOUT+|
|SDI||Bank 2, ADC_SDI|
|SDO||Bank 2, ADC_SDO|
|SCK||Bank 2, ADC_SCK|
|CNV||Bank 2, ADC_CNV|
|Designator||Color||Connected to||Active Level||Note|
|D2...9||Red||LED1...8||Active High||User LEDs|
|D10||Red||CONF_DONE||Active Low||Configuration DONE LED|
|D1||Green||3.3V||Active High||After power on it will be on|
|S2||USER_BTN||User push button||Connected to Bank 8|
|Clock Source||Schematic Name||Frequency||Note|
|Microchip MEMS Oscillator, U7||CLK12M||12.00 MHz|
Connected to FTDI FT2232 U3, pin 3
Connected to FPGA SoC bank 2, pin H6
Power and Power-On Sequence
To power-up the module, power supply with minimum current capability of 1A is recommended.
|Intel MAX 10 10M08 FPGA SoC||TBD*|
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) will be on.
|Connector Designator||VCC / VCCIO Schematic Name|
Absolute Maximum Ratings
|VCC_ONE||Supply voltage for core and periphery through on-die voltage|
|-0.5||3.9||V||Intel MAX 10 datasheet|
Supply voltage for input and output buffers
|-0.5||3.9||Intel MAX 10 datasheet|
|VCCA||Supply voltage for phase-locked loop (PLL) regulator and ADC||-0.5||3.9||Intel MAX 10 datasheet|
|V_AN_IN||Analog Input Voltage on ADC IC U15 pins||–0.3||5.4||V||AD4003BCPZ datasheet|
|V_REF||Analog reference voltage on IC U15||-0.3||6||V||AD4003BCPZ datasheet|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
VIN supply voltage (5.0V nominal)
|VCC_ONE||3.135||3.456||V||see Intel MAX 10 datasheet|
|VCCIO||3.135||3.456||V||see Intel MAX 10 datasheet|
|VCCA||3.135||3.456||V||see Intel MAX 10 datasheet|
|V_AN_IN||-0.1||5.1||V||see AD4003BCPZ datasheet|
|V_REF||2.4||5.1||V||see AD4003BCPZ datasheet|
Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.22 mm.
Currently Offered Variants
Hardware Revision History
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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