Quartus Project Delivery

Quick Start

The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.

The "normal" Quartus project will be generated in the subfolder "/quartus/" and the additional software part will be generated in the subfolder "/sdk/" after executing scripts.

There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects.

If you use our prepared batch files for project creation do the following steps:

1. open "design_basic_settings.cmd" with text editor and set correct quartus path. 
2. run "create_project_win.cmd".

See  Reference Design: Getting Started for more details.

Zip Project Delivery

Zip Name Description

Last supported Release

Currently limitations of functionality

• • • no current limitations of functionality

Directory structure

Command Files

Windows Command Files

TE-TCL-Extensions

Design Environment: Usage

Reference-Design: Getting Started

• Install Quartus Prime 18.1 Lite Edition
• Automatically configuration of the reference-designs:
  • Run "create_project_win.cmd" and follow instructions.
    • • "design_basic_settings.cmd" will be configured over this menu
• Manual Configure the reference-design:
  • Open “design_basic_settings.cmd” with a text-editor:
        a. Set correct Quartus Environment:
            @set QUADIR=C:/intelFPGA_lite
            @set QUARTUS_VERSION=18.1
            Program settings will be search in :
            %QUADIR%/%QUARTUS_VERSION%/quartus/
           %QUADIR%/%QUARTUS_VERSION%/nios2eds/
            Example directory: c:/intelFPGA_lite/18.1/
            Attention: Scripts are supported only with predefined Quartus Version!
• Create and compile project:
  • select "c" to create project
  • if project already exists, choose between "y" for delete and create project again or "n" to keep project
  • after project ist created or project already exists, select "m" to compile project

• Programming FPGA or flash memory with prebuilt files:

  • Connect your Hardware-Modul with PC via JTAG.

  • Select "p" and press enter
  • Quartus Programmer will be open
  • Select "Add File..." and open correct file from /prebuilt/<device_list_shortname>/programming_files/
  • Start programming FPGA or flash memory

Basic Design Settings

Initialise TE-scripts on Vivado/LabTools

• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      
      • for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
      • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
        
    • Press Enter
    • A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source ../scripts/reinitialise_all.tcl
      

Use predefined TE-Script functions

• Variant 1 (recommended):
  • Typ function on Vivado TCL Console, ex.: TE::help
  • TE::help
    
    • Show all predefined TE-Script functions.
  • TE:<functionname> -help 
    
    • Show short description of this function.
    • Attention: If -help argument is set, all other args will be ignored. 
• Variant 2:
  • Create your own function Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push +
    • Type Name ex.: Run SDK
      
    • Press Enter
      
    • Select Run command and insert function:
      • Variante 1 (no Vivado request window for args):
        • insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
      • Variant 2 (Vivado request window for args):
        • insert function, ex.:TE::sw_program_zynq
        • Press Define Args...
        • For every arg:
          
          • Push
          • Typ Name, Comment, Default Value and set optional
          • Press Enter
            
          • Example for args:
            • Push
            • Index, Key Name, -swapp,
            • Push
            • Appname, Arg, hello_world,
              
          •  
    • Press Enter
    • A new Button is shown on the Vivado Gui.

Hardware Design

Device list CSV Description

Device list csv file is used for TE-Scripts only.

SDC Conventions

• All *.sdc from <design_name>/source_files/quartus/ are load into the quartus project on project creation.

Advanced Usage

Attention not all features of the TE-Scripts are supported in the advanced usage!

User defined device list csv file

To modifiy current deivce list csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TEI0001_devices.csv as TEI0001_devices_mod.csv. Scripts used modified csv instead of the original file.

See Chapter Board Part Files for more information.

User defined Settings

Vivado settings:

Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.

Script settings:

Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.

Design settings:

Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/design_settings.tcl". This file will be loaded automatically on script initialisation.

ZIP ignore list:

Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.

SDSOC settings:

SDSOC settings will are deposited on the following folder: "<design_name>/settings/sdsoc"

User defined TCL Script

TCL Files from "<design_name>/settings/usr" will be load automaticaly on script initialisation.

SDSOC-Template

SDSOC description and files to generate SDSoC project are deposited on the following folder: "<design_name>/settings/sdsoc"

HDL-Design

HDL files can be saved in the subfolder "<design_name>/hdl/" as single files or <design_name>/hdl/folder/ and all subfolders or "<design_name>/hdl/<shortname>" and all subfolders of "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv.  A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".

To set file attributes, the file name must include "_simonly_" for simulation only and "_synonly_" for synthese only.

RTL-IP-cores (*.xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.

Checklist / Troubleshoot

1. Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
2. Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
3. Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
4. Win OS only: Use short path name, OS allows only 256 characters in normal path.
5. Linux OS only: Use bash as shell and add access rights to bash files. Check with "ls ls /bin/sh". It should be desplay: /bin/sh -> bash. Access rights can be changed with "chmod"
6. Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
7. Did you have the newest reference design build version? Maybe it's only a bug from a older version.
8. Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
9. On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation problem) and the scripts canceled. Please try again. 
   
10. If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ",  the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)

References

1. Vivado Design Suite User Guide - Getting Started  (UG910)
2. Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
3. Vivado Design Suite User Guide - I/O and Clock Planning (UG899)
4. Vivado Design Suite User Guide - Programming and Debugging (UG908)
5. Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
6. SDSoC Environment User Guide - Getting Started (UG1028)
7. SDSoC Environment -  User Guide (UG1027)
8. SDSoC Environment User Guide - Platforms and Libraries (UG1146)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older revision number.