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Overview

TEB0707 SC CPLD design for MAX10 with designator U6:  10M08SAU169C8G.

Feature Summary

• Levelshifting/MUX of Signals
  
  • CRUVI Low Speed  (J13)
  • CRUVI 3.3V signals on High Speed CA, CB, CC (J10, J11, J12)
• JTAG/ UART forward to 4x5 module
• Module control pins
• USR LEDs
• Button and Dips
• Power sequenzing
• IO Voltage selection

Firmware Revision and supported PCB Revision

See Document Change History.

Product Specification

Port Description

Level shifting/MUX

In this Firmware Version CRUVI Low Speed connector CA has four signals configured as input and another four as output. Depending on the connectors and signals used/needed this can be changed by customizing and updateing the firmware. Also the 3.3V signals on the three CRUVI High Speed connectors can be utilized in that way. See TEB0707 CPLD Firmware.

X0 <= M_G1_01 ;
X2 <= M_G1_02 ;
X4 <= M_G1_03 ;
X6 <= M_G1_04 ;

M_G1_05 <= X1;
M_G1_06 <= X3;
M_G1_07 <= X5;
M_G1_08 <= X7;

JTAG/ UART forward to 4x5 module

JTAG

Switch with hard wired JTAGEN Dip4 between user mode of pins, which corresponds due to the lines below to SoM JTAG ("OFF", open, 'low') and Max10 CPLD ("ON", closed, 'high')

TDO <= M_TDO;
M_TMS <= TMS;
M_TCK <= TCK;
M_TDI <= TDI;

UART

M_G6_01 <= F_UART_TX; --TX UART to SoM
F_UART_RX <= M_G6_02; --RX UART from SoM

Module control pins

RESIN <= BUTTON0; -- reset SoM
NOSEQ <= net_gnd; -- powermanagement by CPLD is NOT disabled
PROGMODE <= not(DIP3); -- select between CPLD (low, closed, on) on SoM or FPGA/SoC (high, open, off )
EN1 <= net_vcc; --module power always enabled
MODE <= SD_CD ; -- select SD boot mode when card installed ('low'), else QSPI ('high')

Button and Dips

User Button

User button on PL is debounced:
M_G1_20 <= Button1_db;

User Dips:

Dip1 is directly forwarded to a PL IO:
M_G1_16 <= not(DIP1);

Dip2 is used for IO Voltage selection, see IO Voltage selection.
Dip3 is used for JTAG selection, see Module control pins.

LEDs

Status LEDs

The LED D7 and D8 are utilized for board status and power information in the following way:

USR LEDs

User LEDs D1, D2, D3 (green) are connected to PL IOs:

LED3 <= M_G1_19;
LED2 <= M_G1_18;
LED1 <= M_G1_17;

User LEDs D4, D5, D6 (red) are connected to IOs which are located at PL or PS  depending on SoM.

LED4 <= M_G6_04;
LED5 <= M_G6_07;
LED6 <= M_G6_08;

ETH LEDs

Ethernet Jack LEDs are not used in this firmware and are therefore tied to GND.

ETH_LED2 <= net_gnd;
ETH_LED1 <= net_gnd;

Power sequenzing

The M3.3VOUT signal of the SoM is used to Enable  CRUVI power rails  and the SOM IO Voltage:

EN_C5VIN <= M3_3VOUT;
EN_C3_3V <= M3_3VOUT;
EN_IOV <= M3_3VOUT;

IO Voltage selection

Select IOV Voltage of DCDC U3:

VS0 <= not(DIP2);
VS1 <= DIP2;
VS2 <= net_gnd;

"010" selects 1.8V (Dip2 open, "OFF", 'high'). 
"001" selects 2.5V (Dip2 closed, "ON", 'low').

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Revision Changes

Legal Notices