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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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TE0729 Basic-System with Watchdog example via VIO Interface.
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Date | Vivado | Project Built | Authors | Description |
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2018-07-16 | 2018.2 | TE0729-test_board-vivado_2018.2-build_02_20180716161110.zip TE0729-test_board_noprebuilt-vivado_2018.2-build_02_20180716161138.zip | John Hartfiel | initial release |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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Vivado | 2018.2 | needed |
SDK | 2018.2 | needed |
PetaLinux | 2018.2 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
TE0729-02-2IF | 2if | REV02, REV01 | 512MB | 32MB | 2IF-K is the same with head sink | |
TE0729-02-2IR | 2ir | REV02 | 512MB | 32MB | PL ETHs, RTC are no assembled | external ISSI Flash configuration only with SDK possible on 18.2 |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TEB0729 | Used as reference carrier. |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Type | Location | Notes |
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init.sh | <design name>/misc/init_script | Additional Initialization Script for Linux |
<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Not used on this Example.
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R Variant:
Typ | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO |
I2C0 | MIO |
I2C1 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0 | |
TTC0..1 | |
ETH00 | MIO |
USB0 | MIO |
PL-PS IRQ |
# # Common bitgen related settings # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] #set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
# # Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design] |
set_property PACKAGE_PIN F16 [get_ports {FPGA_IO[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_IO[0]}] set_property PACKAGE_PIN H15 [get_ports {WDI_EN[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {WDI_EN[0]}] set_property PACKAGE_PIN R15 [get_ports {WD_HIT[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {WD_HIT[0]}] |
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For SDK project creation, follow instructions from:
Source location: \sw_lib\sw_apps
TE modified 2018.2 FSBL. Xilinx default FSBL on default setup. eMMC selection with FSBL possible.
Changes:
TE modified 2018.2 FSBL
Changes:
Hello TE0729 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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For PetaLinux installation and project creation, follow instructions from:
No changes.
Change platform-top.h
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ "set dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */ #ifdef CONFIG_ZYNQ_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ #define CONFIG_SYS_I2C_MUX_ADDR 0x74 #define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4 #endif |
Note: for R assembly variant, remove ETH1, ETH2 and RTC
/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* AXI ETH PHY0 */ &axi_ethernetlite_0 { local-mac-address = [00 0a 35 00 22 02]; phy-handle = <&phy1>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* AXI ETH PHY1 */ &axi_ethernetlite_1 { local-mac-address = [00 0a 35 00 22 03]; phy-handle = <&phy2>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy2: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* RTC */ &i2c0 { rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; }; |
Activate:
Activate:
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
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No additional software is needed.
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Date | Document Revision | Authors | Description |
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2018-07-13 | v.1 |
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