Overview

Refer to http://trenz.org/te0xyz-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0835 "Test Board" Reference Design

Software Setup

Download RF Analyzer GUI from the following link and install it.

• RF Analyzer

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools

• Vivado Projects - TE Reference Design

• Project Delivery - Xilinx devices

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery - Xilinx devices

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   

2. Press 0 and enter to start "Module Selection Guide"

3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)

4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)

   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note: Select correct one, see also TE Board Part Files

5. Create XSA and export to prebuilt folder

   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt

      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder

6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA

   1. XSA is exported to "prebuilt\hardware\<short name>"

      Note: HW Export from Vivado GUI create another path as default workspace.

   2. Create Linux images on VM, see PetaLinux KICKstart

      1. Use TE Template from /os/petalinux

7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder

   1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"

8. Generate Programming Files with Vitis

   1. Run on Vivado TCL: TE::sw_run_vitis -all

      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"

   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis

      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Xilinx Development Tools

Get prebuilt boot binaries

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell

2. Press 0 and enter to start "Module Selection Guide"

   1. Select assembly version

   2. Validate selection

   3. Select Create and open delivery binary folder

      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot

   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

             optional "TE::pr_program_flash -swapp hello_te0835" possible

4. Copy image.ub on SD-Card

   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries

   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt

5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card

   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries

   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt

2. Set Boot Mode to SD-Boot.

   • Depends on Carrier, see carrier TRM.

3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Hardware Setup

The Hardware contains of a TE0835 module and TEB0835 carrier board and has 8 ADC inputs and 8 DAC outputs.

1. Plug the TE0835 module on the TEB0835 carrier board

2. Install the cooler on the RFSoC chip

   1. Attention: It is strongly recommended that the RFSoC should not be used without heat sink.

3. Connect the micro USB cable to the J29 connector

4. Plug the board on the PCIe port of the PC

5. Plug the prepared SD card on the SD card socket (J28)

6. Connect a cable with SMA or UFL connector to one of the DAC connector( for example DAC0 J9) and feed it back to the related ADC input (for example ADC0 J1)

7. (optional) A signal generator can be used to feed desired sinal to ADC input.

8. (optional) An oscilloscope can be used to monitor the output signal of DAC.

Usage

1. Prepare HW like described on section TE0835 Test Board#Hardware Setup

2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Note: See TRM of the Carrier, which is used.

4. Power On PCB

   Note: 1. Zynqmp RFSoC Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)

   1. Speed: 115200

   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   

   1. User Name: root

   2. Password: root

3. You can use Linux shell now.

   1. I2C Bus type: i2cdetect -y -r 0

      1. Bus 0 up to 5 possible

   2. RTC check: dmesg | grep rtc

   3. ETH0 works with udhcpc

   4. USB type  "lsusb" or connect USB2.0 device

   5. PCIe Bus type: "lspci"

      1. PCIe device should be seen in the console 

4. Option Features

   1. Webserver to get access to Zynqmp RFSoC
      

      1. insert IP on web browser to start web interface

   2. init.sh scripts

      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
         

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Monitoring:

  • The output frequency  of MMCM blocks can be monitored.

    • Set radix from VIO signals to unsigned integer.

    • The tempreature of ARM processor and FPGA can be measured too.

RF Analyzer

1. Open the RF Analyzer GUI

2. Click on Connect button

3. Adjust the desired JTAG frequency (for example 30MHZ)

4. Give the generated bitstream file path

5. Click on Download Bitstream button to load the Bitstream file on the FPGA

6. When downloading is finished, click on Select Target button

7. After initilalisation, all ADCs/DACs tiles are visible

8. Click on desired DAC tile and choose a DAC (for example DAC0)

9. Adjust desired DAC properties (for example output frequency)

10. Click on Generate button to generate the signal in output of DAC

11. Click on the related ADC tile and choose the related ADC (for example ADC0)

12. Click on Acquire button to aqcuire the input signal

13. The spectum of the DAC output signal can be seen now. The signal can be visible in time domain too.

    1. Tip: In menu Window click on Multiview to see all of DACs and ADCs simultaneously.

As an example the GUi should be seen after initialization as below:

For example, when all DACs are in operation, the GUI can be seen as below:

For example, when all ADCs are in operation, the GUI can be seen as below:

System Design - Vivado

Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

Design specific constrain

Software Design - Vitis

For SDK project creation, follow instructions from:

Vitis

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)

• Add Files:  te_*

• General Changes: 

  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*

  • Si5395 on the TE0835 RFSoC module configuration

  • Si5395 on the TEB0835 carrier board configuration

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c

• General Changes:

  • Display FSBL Banner

  • Set FSBL Boot Mode to JTAG

  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0835

Hello TE0835 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

U-Boot

Start with petalinux-config -c u-boot

Changes:

• CONFIG_ENV_IS_NOWHERE=y

• # CONFIG_ENV_IS_IN_SPI_FLASH is not set

• CONFIG_I2C_EEPROM=y

• CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

• CONFIG_SYS_I2C_EEPROM_ADDR=0

• CONFIG_SYS_I2C_EEPROM_BUS=0

• CONFIG_SYS_EEPROM_SIZE=256

• CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

• CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

• CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

• CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Change platform-top.h:

Device Tree

Kernel

Start with petalinux-config -c kernel

Changes:

• CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

• CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

• CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

• CONFIG_i2c-tools=y

• CONFIG_busybox-httpd=y (for web server app)

• CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

See: \os\petalinux\project-spec\meta-user\recipes-apps\

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynqmp RFSoC access. Need busybox-httpd

Additional Software

No additional software is needed.

SI5395 of RFSoC module

File location <design name>/misc/Si5395/Si5395-*-835-*.slabtimeproj

General documentation how you work with these project will be available on Si5395

SI5395 of carrier board

File location <design name>/misc/Si5395/Si5395-*-B835-*.slabtimeproj

General documentation how you work with these project will be available on Si5395

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices