Template Revision 3.0Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
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RF Analyzer GUI | Board TE0835 ( RFSoC U1) | TEB0835 | ||||
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Tile /Converter | SoC Pin Name | SoC Pin Number | B2B | Signal Name | Connector Designator | Connector Type |
ADC Tile 0-ADC 01 | ADC0_P/ADC0_N | AK2/AK1 | 31/29 | ADC0_P/ADC0_N | J1 | SMA |
ADC Tile 0-ADC 23 | ADC1_P/ADC1_N | AH2/AH1 | 43/41 | ADC1_P/ADC1_N | J2 | UFL |
ADC Tile 1-ADC 01 | ADC2_P/ADC2_N | AF2/AF1 | 49/47 | ADC2_P/ADC2_N | J3 | SMA |
ADC Tile 1-ADC 23 | ADC3_P/ADC3_N | AD2/AD1 | 59/61 | ADC3_P/ADC3_N | J4 | UFL |
ADC Tile 2-ADC 01 | ADC4_P/ADC4_N | AB2/AB1 | 67/65 | ADC4_P/ADC4_N | J5 | SMA |
ADC Tile 2-ADC 23 | ADC5_P/ADC5_N | Y2/Y1 | 79/77 | ADC5_P/ADC5_N | J6 | UFL |
ADC Tile 3-ADC 01 | ADC6_P/ADC6_N | V2/V1 | 85/83 | ADC6_P/ADC6_N | J7 | SMA |
ADC Tile 3-ADC 23 | ADC7_P/ADC7_N | T2/T1 | 97/95 | ADC7_P/ADC7_N | J8 | UFL |
DAC Tile 0-DAC 0 | DAC0_P/DAC0_N | N2/N1 | 103/101 | DAC0_P/DAC0_N | J9 | SMA |
DAC Tile 0-DAC 1 | DAC1_P/DAC1_N | L2/L1 | 109/107 | DAC1_P/DAC1_N | J10 | UFL |
DAC Tile 0-DAC 2 | DAC2_P/DAC2_N | J2/J1 | 121/119 | DAC2_P/DAC2_N | J11 | SMA |
DAC Tile 0-DAC 3 | DAC3_P/DAC3_N | G2/G1 | 127/125 | DAC3_P/DAC3_N | J12 | UFL |
DAC Tile 1-DAC 0 | DAC4_P/DAC4_N | E2/E1 | 133/131 | DAC4_P/DAC4_N | J13 | UFL |
DAC Tile 1-DAC 1 | DAC5_P/DAC5_N | C2/C1 | 139/137 | DAC5_P/DAC5_N | J14 | UFL |
DAC Tile 1-DAC 2 | DAC6_P/DAC6_N | B4/A4 | 151/149 | DAC6_P/DAC6_N | J15 | UFL |
DAC Tile 1-DAC 3 | DAC7_P/DAC7_N | B6/A6 | 157/155 | DAC7_P/DAC7_N | J16 | UFL |
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----------------------------------------------------------FPGA ExamplescuMCS Firmware to configure SI5338 and Reset System.srec_spi_bootloaderTE modified 2019.2 SRECBootloader to load app or second bootloader from flash into DDRDescriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
----------------------------------------------------------Zynq Example:zynq_fsblTE modified 2019.2 FSBLGeneral:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBLGeneral:
ZynqMP Example:----------------------------------------------------------zynqmp_fsblTE modified 2019.2 FSBLGeneral:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBLGeneral:
zynqmp_pmufwXilinx default PMU firmware.----------------------------------------------------------General Example:hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
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