Design Name always "TE Series Name" + Design name, for example "TEM0007 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
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Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
*used as reference |
The Design requires one of the following carriers:
*used as reference |
Additional hardware requirements:
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Notes :
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For further insight into the structure of a Trenz Reference Design Download and usage of its content in general , please follow the link Project Delivery - Microchip devices
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Notes :
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Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.
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Reference design is available on:
Notes :
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Trenz Electronic provides a TCL project generation based on Microchip's Design Flow where possible.
See also:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
The Libero SoC Hardware Design Project for this board is delivered as a TCL script which utilizes the Libero SoC Command API .
The script Libero SoC Project will be generated into the folder "<project folder> / libero_<Variant short name>".
E:\Microchip_svn\23.1\designs\TEM0007\test_board\scripts\ Generate_TEM0007_Hardware-Design_in_Libero_SoC_v2023.1 --------------- Start : design_subversion_setup.tcl --------------- ### Autostart via System Path Variable "acttclsh" ### - Probing for acttclsh.exe "where acttclsh" INFORMATION: Es konnten keine Dateien mit dem angegebenen Muster gefunden werden. ### Autostart via System Path Variable "tclsh" ### - Probing for tclsh.exe "where tclsh" INFORMATION: Es konnten keine Dateien mit dem angegebenen Muster gefunden werden. ### Autostart searching for default Libero SoC installation ### - Searching for acttclsh.exe List of Libero_SoC installations in c:\Microchip\ and their TCL Shell(s) : Libero_SoC_v2023.1 c:\Microchip\Libero_SoC_v2023.1\Designer\bin\acttclsh.exe # Autostart via Libero_SoC TCL Shell # - Executing script Using TCL Shell c:\Microchip\Libero_SoC_v2023.1\Designer\bin\acttclsh.exe Processing script parameters : Setting dict key:windowWidth value:118 pair Console window has width : 118 Parameter path not an argument to this script : key "path" not known in dictionary -------------------- TEM0007 test_design -------------------- TCL Version : 8.6 This script generates the Hardware Design for the Trenz Electronic module series TEM0007. The Hardware Design itself is a Microchip Libero SoC Design Suite project. This script requires a Libero SoC installation equal or later than : Libero SoC Version 2023.1 [When the built stops with the error message : Error: Cannot find Spirit core configuration file for vendor:.. library:.. name:.. version:... Error: The command 'create_and_configure_core' failed. Upgrading the Libero SoC Soft Core Catalog can help . To do so , use the script option to upgrade the cores later in this script . Manually this is done via : Open Libero and go to the Soft Core Catalog via "View > Windows > Catalog" and press the button "Download them now!" .] Found Libero SoC installations in default folder : C:/Microchip/Libero_SoC_v2023.1 C:/Microsemi/Libero_SoC_v2021.2 C:/Microsemi/Libero_SoC_v12.4 ### Select from the following options which Libero SoC version should be used to build the design : Option 0 : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe Option 1 : Enter path to your Microchip or Libero SoC installations folder The script selects automatically the Libero exe Option 2 : Enter the full path to your Libero SoC exe Option 3 : Exit the script Selection : (0 to 3) 0 Using Libero SoC @ : C:/Microchip/Libero_SoC_v2023.1/Designer/bin/libero.exe ### Do you wish to update the Libero SoC Soft Cores ? (Yes = y/t/1 or No = n/f/0) : 1 Updating soft cores started Console Mode = Downloading Microchip:SolutionCore:YCbCrtoRGB:4.6.0... OK Info: Core 'Microchip:SolutionCore:YCbCrtoRGB:4.6.0' was successfully downloaded. Downloading Microsemi:MiV:MIV_RV32:3.1.200... OK ### Hardware Designs are available for these variants : ID : PRODID FAMILY DEVICE PACKAGE SPEED TEMP SHORTNAME FLASH_SIZE DDR_SIZE PCB_REV NOTES 1 : TEM0007-01-S002 "PolarfireSoC" MPFS250T_ES FCVG484 STD EXT 25_1E0_ES_1GB NA 1GB REV01 "produced prototyp" 2 : TEM0007-01-CHE11-A "PolarfireSoC" MPFS250T FCVG484 STD EXT 250_1E_1GB NA 1GB REV01 "produced" 3 : TEM0007-01-CAA11-A "PolarfireSoC" MPFS025T FCVG484 STD EXT 025_1E_1GB NA 1GB REV01 "currently factory order 5555" 4 : TEM0007-01-CAD11-A "PolarfireSoC" MPFS025T FCVG484 -1 IND 025_1I_1GB NA 1GB REV01 "currently ERP only" 5 : TEM0007-01-CBD11-A "PolarfireSoC" MPFS095T FCVG484 -1 IND 095_1I_1GB NA 1GB REV01 "currently factory order 5555" 6 : Exit script Enter ID number of your board (1 to 6) : 1 ### Which Soft Core Versions should be used to generate the Hardware Design ? (The design can be generated with local sources , when a Libero SoC version with the same major version is used) Option 0 : Download the newest soft core versions Option 1 : Download the soft cores versions , for which the Hardware Design was verified Option 2 : Use a local copy of the soft cores sources , which the Hardware Design was verified for Option 3 : Exit script Selection : (0 to 3) 1 ### Folder overwrite protection . Checking for existing Libero SoC project folder named "libero_25_1E0_ES_1GB" : Found existing Libero SoC project folder "libero_25_1E0_ES_1GB" Select how to proceed : Option 0 : Overwrite this Libero SoC project folder Option 1 : Enter new Libero SoC project folder name Option 2 : Exit script Selection : (0 to 2) 0 ### Which Hardware Description Language do you prefer : VHDL or Verilog ? Option 0 : VHDL Option 1 : Verilog Option 2 : Exit script Selection : (0 to 2) 0 ### Determine expected Libero SoC Project path lengths : Expected maximum Libero SoC Project path length : root + project name + relatvive path = path length 48 + 21 + 135 = 204 The root path length is well below the Libero SoC Path Length Limit of 250 chars . The Hardware Designs Build / Synthesis or Bitstream generation should succeeded . ### Building the hardware design started at 17:17:38 , this will take some minutes . [In rare cases, this console may not advance from here on . Visible through a not blinking cursor. Wait some minutes , focus the console and press space, the script will continue .] ### Checking the results via log evaluation : Hardware design generation was successfull The projects path is : E:/Microchip_svn/23.1/designs/TEM0007/test_board/libero_25_1E0_ES_1GB The build log "libero_25_1E0_ES_1GB_build_2024.02.19_171738.log" was saved to : E:/Microchip_svn/23.1/designs/TEM0007/test_board/log ### Hardware Design Compilation and Bitstream Generation : Do you want the these files to be build and exported ? Selection (Yes = y/t/1 or No = n/f/0) : 1 Generating folders for prebuilt files Folder bitstream already exists and will be overwritten Folder flashpro already exists and will be overwritten ### Executing the prebuilt started at 17:22:24 , this will take some minutes . ### Checking the results via log evaluation : Generation and export of Prebuilt Files was successfull The files have been exported to the subfolders bitstream and flashpro inside : E:/Microchip_svn/23.1/designs/TEM0007/test_board/prebuilt/hardware/25_1E0_ES_1GB The prebuilt log "libero_25_1E0_ES_1GB_prebuilt_2024.02.19_171738.log" was saved to : E:/Microchip_svn/23.1/designs/TEM0007/test_board/log ### Open the generated Libero Soc TEM0007 test_design ? Selection (Yes = y/t/1 or No = n/f/0) : 1 Please press any key . . . |
In test board reference zip file the job files in prebuilt folder consist of HSS generated hex file. The following instruction are only to know , how the final job file is prepared and regenerated. |
Get prebuilt boot binaries
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Describe how to programm the bitstream of the design onto the board or carrier . |
Check module and carrier TRMs for proper HW configuration before you try any design. |
There is two ways to program bitstream file on FPGA. The Bitstream can be programmed into the FPGA / SOC by Libero SoC or Flash Pro Express :
Describe how to programm the bitstream of the design onto the board or carrier . |
The eNVM is a user non-volatile flash memory that can be programmed independently. There is two methods to program eNVM:
To program HSS *.hex file on FPGA:
The HSS generated hex file can be attached to bitstream file. For more information see Design Flow
To program the eNVM in Flashpro Express see Using FlashPro Express
Get prebuilt boot binaries
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This module supports SD card boot and JTAG boot mode. The selection between them will be done in HSS, so there is no need to select the boot mode via Dip Switches .
Prepare SD card as follows for SD card boot mode:
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Not used on this example.
Select COM Port of linux console (UART1)
Win OS: see device manager Linux OS: see dmesg | grep tty (UART is *USB1) |
Login data:
Note: Wait until Linux boot finished |
tem0007 login: root |
You can use Linux shell now.
i2cdetect -l (check I2C Bus) ifconfig -a (ETH0 check) lsusb (USB check) |
Note:
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The Block Design of a board variant or revision may differ slightly depending on the assembly variant.
List of active interfaces of the design . Please update the list |
Activated interfaces:
Type | Note |
DDR | -- |
EMAC0 | -- |
GPIO1 | -- |
GPIO2 | -- |
I2C0 | -- |
I2C1 | -- |
SPI0 | -- |
QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB | -- |
Insert all constraint files which the Hardware Design uses here . If a division into sub chapters is necessary , the subchapters "Basic module constrains" and "Design specific constrain" have been added . Delete them not necessary . |
set_iobank -bank_name Bank0 \ -vcci 1.80 \ -fixed true \ -update_iostd true set_iobank -bank_name Bank1 \ -vcci 3.30 \ -fixed true \ -update_iostd true set_iobank -bank_name Bank4 \ -vcci 3.30 \ -fixed true \ -update_iostd true |
set_io -port_name REF_CLK_PAD_P \ -pin_name J19 \ -DIRECTION INPUT set_io -port_name REF_CLK_PAD_N \ -pin_name J20 \ -DIRECTION INPUT |
set_io -port_name GPIO_2_2 \ -pin_name D9 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_3 \ -pin_name D6 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_4 \ -pin_name C6 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_7 \ -pin_name B5 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_8 \ -pin_name C5 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_9 \ -pin_name C4 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_11 \ -pin_name F16 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_12 \ -pin_name D14 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_13 \ -pin_name E14 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name GPIO_2_14 \ -pin_name B4 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT |
set_io -port_name MAC_0_MDC \ -pin_name H6 \ -fixed true \ -DIRECTION OUTPUT \ -io_std LVCMOS33 set_io -port_name MAC_0_MDIO \ -pin_name J3 \ -fixed true \ -DIRECTION INOUT \ -io_std LVCMOS33 |
set_io -port_name MMUART_0_TXD \ -pin_name C2 \ -fixed true \ -DIRECTION OUTPUT \ -io_std LVCMOS33 set_io -port_name MMUART_0_RXD \ -pin_name D3 \ -fixed true \ -DIRECTION INPUT \ -io_std LVCMOS33 |
set_io -port_name MMUART_1_TXD \ -pin_name H5 \ -fixed true \ -DIRECTION OUTPUT \ -io_std LVCMOS33 set_io -port_name MMUART_1_RXD \ -pin_name H2 \ -fixed true \ -DIRECTION INPUT \ -io_std LVCMOS33 |
set_io -port_name USER_PWM0 \ -pin_name D7 \ -fixed true \ -io_std LVCMOS33 \ -RES_PULL Down \ -DIRECTION OUTPUT set_io -port_name USER_IN0 \ -pin_name V19 \ -fixed true \ -DIRECTION INPUT set_io -port_name USER_OUT0 \ -pin_name AB19 \ -fixed true \ -DIRECTION OUTPUT # JM2-Pin73/ JB2-Pin74 / B13_L16_N (Suitable for modified TE0703) #set_io -port_name RESETN \ -pin_name H13 \ -fixed true \ -io_std LVTTL \ -CLAMP_DIODE OFF \ -RES_PULL Up \ -DIRECTION INPUT # JM2-Pin55 TEM0007 / JB2-Pin56 (SRST) TEB2000 / B13_L9_P set_io -port_name RESETN \ -pin_name E15 \ -fixed true \ -io_std LVTTL \ -CLAMP_DIODE OFF \ -RES_PULL Up \ -DIRECTION INPUT |
set_io -port_name QSPI_CLK \ -pin_name C10 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name QSPI_DATA_0 \ -pin_name D13 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name QSPI_DATA_1 \ -pin_name B12 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name QSPI_DATA_2 \ -pin_name C9 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name QSPI_DATA_3 \ -pin_name C12 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT set_io -port_name QSPI_SEL \ -pin_name A13 \ -fixed true \ -io_std LVCMOS33 \ -DIRECTION INOUT |
create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3} -multiply_by 2 -source [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C1_0/PF_CLK_DIV_C1_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C1_0/PF_CLK_DIV_C1_0/I_CD/A } ] [ get_pins { CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C1_0/PF_CLK_DIV_C1_0/I_CD/Y_DIV } ] set_false_path -through [ get_nets { FIC_0_PERIPHERALS_1/DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -through [ get_nets { FIC_0_PERIPHERALS_1/FIC0_INITIATOR_inst_0/ARESETN* } ] |
Note:
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Describe How to generate / compile the application . Use sections for different applications . E.g. : |
---------------------------------------------------------- General Example: |
Template location: <project folder>/softconsole_source/
Hart Software Services (HSS) code on PolarFire SoC, is comprised of two portions:
A superloop monitor running on the E51 minion processor, which receives requests from the individual U54 application processors to perform certain services on their behalf.
A Machine-Mode software interrupt trap handler, which allows the E51 to send messages to the U54s, and request them to perform certain functions for it related to rebooting a U54.
The HSS performs boot and system monitoring functions for PolarFire SoC. The HSS is compressed (DEFLATE) and stored in eNVM. On power-up, a small decompressor wrapper inflates the HSS from eNVM flash to L2-Scratchpad memory and starts the HSS.
Note that HSS can be changed for every TEM0007 variant. Therefore the hex file for every variant is created and saved in the following path of test design folder separately: (<project folder>/prebuilt/soctware/<short name of the module variant>)
To create HSS file for a desired module variant the saved MSS configuration xml file in "<softconsole workspace folder>/ hart-software-services-<HSS version>/board/TEM0007/soc_fpgs_design/xml/" must be matched for its related xml file. To do it:
Describe how to generate / compile the Linux distribution . E.g. : |
The host pc must be prepared for using the yocto. For more information about host pc setup for yocto and the required packets please refer to System Requirements
Trenz electronic has developed his own BSP for Microchip devices same as polarfire soc in Yocto. In the following will be explained the folders in detail.
meta-trenz-polarfire-bsp Folder | Description |
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recipes-apps* | Consists of start up application for executing of init.sh by booting. More application can be saved in this folder. |
recipes-bsp | Consists of uboot required files same as *.bbappend files, device tree and etc. |
recipes-core | Consists of *.bb file for Trenz defined image version. This file consists of required packets or files that must be installed. |
recipes-kernel | Consists of kernel required files same as *.bbappend files, device tree, config files and etc. |
recipes-tools | Consists of a *.bbappend file. |
tools | Consists of manifest xml file to define meta data that are required. |
wic | Consists of *.wks file that describes disk image properties. |
*Note: In this version is not used.
In the following table exists more information about required packets and supported version.
Meta data | Supported Version | Description |
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meta-riscv | Kirkstone | |
openembedded-core | Kirkstone | |
meta-openembedded | Kirkstone | |
meta-polarfire-soc-yocto-bsp | 2022.11 |
Trenz BSP contains of a shell script. If this shell script is executed , all required processes for making a linux image file will be executed automatically. The user needs only to write the generated image file on the SD card. To prepare the image file :
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" <trenz BSP folder>/prebuilt/boot/yocto/SD_Card.zip "
Please update the listing of ... . |
File location: <trenz BSP folder>/recipes-bsp/u-boot/
Changes:
CONFIG_PHY_MARVELL=y
CONFIG_DEFAULT_DEVICE_TREE="tem0007"
CONFIG_DEFAULT_FDT_FILE="tem0007.dtb"
CONFIG_OF_LIST="tem0007"
CONFIG_DM_GPIO=y
CONFIG_CMD_GPIO=y
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=y
CONFIG_LOG_CONSOLE=y
CONFIG_NVMEM=y → to be able to read MAC vom EEPROM
CONFIG_DM_RTC=y
Please insert the Device Tree files into the Codeblocks below . Add or remove Codeblocks if necessary |
// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2020 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ / { aliases { cpu1 = &cpu1; cpu2 = &cpu2; cpu3 = &cpu3; cpu4 = &cpu4; }; }; |
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2021 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ /dts-v1/; #include "microchip-mpfs.dtsi" #include "dt-bindings/gpio/gpio.h" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 / { model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { serial1 = &uart1; ethernet0 = &mac0; spi0 = &qspi; }; chosen { stdout-path = "serial1"; }; cpus { timebase-frequency = <RTCCLK_FREQ>; }; ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; clocks = <&clkcfg CLK_DDRC>; status = "okay"; }; usb_phy: usb_phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; reset-names = "OTG_RST"; }; }; &uart1 { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-mmc-highspeed; cap-sd-highspeed; cd-debounce-delay-ms; card-detect-delay = <200>; // mmc-ddr-1_8v; // mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &i2c1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; //compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; &refclk { clock-frequency = <125000000>; }; &mac1 { status = "disabled"; }; &mac0 { status = "okay"; phy-mode = "sgmii"; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &qspi { status = "okay"; num-cs = <1>; flash0: spi-nor@0 { compatible = "spi-nor"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <20000000>; spi-cpol; spi-cpha; }; }; &usb { status = "okay"; dr_mode = "otg"; // dr_mode = "host"; phys = <&usb_phy>; }; |
// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; #include "mpfs.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> /* Clock frequency (in Hz) of the rtcclk */ #define MTIMER_FREQ 1000000 / { #address-cells = <2>; #size-cells = <2>; model = "Trenz TEM0007"; compatible = "trenz,tem0007","microchip,mpfs"; aliases { ethernet0 = &mac0; serial0 = &mmuart0; serial1 = &mmuart1; serial2 = &mmuart2; serial3 = &mmuart3; serial4 = &mmuart4; }; chosen { stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = <MTIMER_FREQ>; }; //******************************************************// ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; fabricbuf0ddrc: buffer@A0000000 { compatible = "shared-dma-pool"; reg = <0x0 0xA0000000 0x0 0x2000000>; no-map; }; }; udmabuf0 { compatible = "ikwzm,u-dma-buf"; device-name = "udmabuf-ddr-c0"; minor-number = <0>; size = <0x0 0x2000000>; memory-region = <&fabricbuf0ddrc>; sync-mode = <3>; }; //******************************************************// usb_phy: usb_phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; reset-names = "OTG_RST"; }; soc { dma-ranges = <0 0 0 0 0x40 0>; }; }; &gpio1 { status = "okay"; }; &gpio2 { interrupts = <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>; status = "okay"; }; &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; //compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; &mac0 { status = "okay"; phy-mode = "sgmii"; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &mbox { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-mmc-highspeed; // mmc-ddr-1_8v; // mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &mmuart1 { status = "okay"; }; &mmuart2 { status = "okay"; }; &mmuart3 { status = "okay"; }; &mmuart4 { status = "okay"; }; &qspi { status = "okay"; num-cs = <1>; }; &refclk { clock-frequency = <125000000>; }; &spi0 { status = "okay"; }; &usb { status = "okay"; dr_mode = "otg"; // dr_mode = "host"; phys = <&usb_phy>; }; &syscontroller { status = "okay"; }; |
Please update the listing of ... . |
File location: <trenz BSP folder>/recipes-kernel/linux/
Changes:
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="earlycon=sbi root=/dev/mmcblk0p3 rootwait uio_pdrv_genirq.of_id=generic-uio"
CONFIG_EEPROM_AT24=y
CONFIG_NVMEM=y
CONFIG_NVMEM_SYS=y
CONFIG_REGMAP_I2C=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_CLASS=y
CONFIG_NEW_LEDS=y
CONFIG_GPIOLIB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=n
CONFIG_MTD_UBI=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_UBIFS_FS=y
CONFIG_MTD_SPI_NOR=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y
CONFIG_MFD_SENSEHAT_CORE=m
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_JOYSTICK=y
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_AUXDISPLAY=y
CONFIG_SENSEHAT_DISPLAY=m
CONFIG_HTS221=m
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_MAGN_3AXIS=m
#CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
Please update the listing of ... . |
Image recipe for minimal console image
File location: <trenz BSP folder>/recipes-core/images/
Image recipes:
Added packages/recipes:
startup
iputils-ping
expect
rsync
rng-tools
iperf3
devmem2
can-utils
usbutils
pciutils
polarfire-soc-linux-examples
dt-overlay-mchp
libgpiod
libgpiod-tools
libgpiod-dev
i2c-tools
vim vim-vimrc
net-tools
htop
iw
python3
python3-pip
python3-flask
python3-flask-dev
python3-werkzeug
libudev
glib-2.0
sqlite3
dtc
cmake
tar
wget
zip
mtd-utils
mtd-utils-ubifs
Please update the listing of ... . |
Used filesystem: Root file system (RootFS)
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