Table of contents
|
Name | Direction | Pin | Description |
---|---|---|---|
JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one:CPLD, logical zero: FPGA) |
M_TMS | IN | 29 | JTAG from B2B connector |
M_TCK | IN | 30 | JTAG from B2B connector |
M_TDI | IN | 32 | JTAG from B2B connector |
M_TDO | OUT | 1 | JTAG from B2B connector |
C_TMS | OUT | 21 | JTAG to FPGA |
C_TCK | OUT | 17 | JTAG to FPGA |
C_TDI | OUT | 23 | JTAG to FPGA |
C_TDO | IN | 20 | JTAG to FPGA |
XIO | IN | 4 | FPGA access W22 PIN |
FPGA_IO | INOUT | 10 | FPGA access U22 PIN |
RESIN | IN | 16 | RSIN from B2B connector |
DONE | IN | 28 | FPGA Configuration DONE_0 Pin |
PROG_B | OUT | 27 | FPGA Configuration PROGRAM_B_0 Pin |
PGOOD | OUT | 12 | PGOOD to B2B connector |
PG_SENSE | IN | 25 | 3.3V |
EN1 | IN | 11 | Power Enable from B2B Connector |
LED1 | OUT | 8 | Module LED D1 (Green) |
LED2 | OUT | 9 | Module LED D2 (Red) |
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN ( (ogical one:CPLD, logical zero: FPGA).
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
2016-04-11 |
| REV01 | REV01, REV02 | Work in progress | |
2016-04-11 |
v.1 | --- | Initial release | ||
All |