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Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0705 for downloadable version of this manual and additional technical documentation of the product. |
The Trenz Electronic TE0705 carrier board provides functionality for testing, evaluation and development purposes of company's 4 x 5 cm SoMs (System on Module). The carrier board is equipped with a broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.
See "4 x 5 cm carriers" page for more information about supported 4 x 5 cm SoMs.
Figure 1: TE0705-04 Block Diagram.
Figure 2: 4 x 5 SoM carrier board TE0705-04.
RJ45 GbE Connector
Micro SD card socket is connected to the B2B connector through a Texas Instruments TXS02612 SDIO Port Expander for voltage translation. The Micro SD card has 3.3V signal voltage level while Xilinx Zynq MIO bank uses 1.8V for VCCIO.
The TE0701 carrier board has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program the System Controller CPLD, Channel B can be used as UART Interface routed to CPLD. There are also 6 additional bus-lanes available for user-specific use.
There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom configuration settings.
| Warning: When using FTDI software tools, the 256 byte user EEPROM can be erased without confirmation. As a consequence, the Digilent license stored in that EEPROM will also be deleted. |
The TE0705 carrier board has two USB connectors:
JTAG access to the CPLD and SoM is provided via mini-USB JTAG interface J7 (FTDI FT2232H) and controlled by DIP switch S3-3.
To enable JTAG port of the CPLD, set switch S3-3 JTAGEN to OFF.
There are eight LEDs (D6, D7, D8, D9, D4, D5, D14, D15) available to the user. All LEDs are red colored and mapped to the on-board System Controller CPLD. Their functions are programmable and depend on the firmware of the System Controller CPLD. For detailed information, please refer to the documentation of the TE0705 System Controller CPLD.
One green LED D22 shows the availability of the 3.3V supply voltage of the TE0705 Carrier Board.
On the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (15) in Figure 1) available. The default switch mapping is as follows:
| Switch | Functionality |
|---|---|
| S3-1 | CM1: Mode pin 1 (routed to Carrier Controller) |
| S3-2 | CM0: Mode pin 0 (routed to Carrier Controller) |
| S3-3 | JTAGEN: Set to ON for normal JTAG operation. Must be moved to OFF position for TE0705 System Controller CPLD update only |
| S3-4 | MIO0: Set MIO0-pin (on MIO0-Bank) on Zynq-modules, else low-active user IO-pin |
Table 1: Configuration of DIP-switch S3.
Additionally, on the TE0705 Carrier Board there is a 4-bit DIP-switch S3 (see (16) in Figure 1) available. The signals of the switch are routed to carrier board's System Controller CPLD and are fully user-configurable depending on a customer developed CPLD firmware. Please refer to the documentation of the TE0705 System Controller CPLD to get information how to put these user-switches in operation.
The switches are connected to pull-up resistors and have a physical high-level of 3.3V on OFF-position.
On the TE0705 Carrier Board there are two push buttons (S1 and S2) and are routed to the System Controller CPLD and available to the user. The default mapping of the push buttons is as follows:
| Name | Default Mapping: | |
|---|---|---|
| S1 | If S1 is pushed, the active-low RESet IN (RESIN) signal will be asserted. Note: This reset can also be forced by the FTDI USB to JTAG interface. | |
| S2 | If S2 is pushed, the active-high Power ON (PON) signal (that is internally pulled-up) will be deasserted, which can be considered as a "RESTART" button to switch off (push button) and on (release button) all on-module power supplies (except 3.3VIN). Note: The capability of the switch to be enabled the first time will become active shortly after Power on Reset (POR).
By closing jumper J4 the PON signal will be permanently deasserted, hence the power FET switch and the DC-DC converters on module will be disabled. |
Table 2: Description of the standard functionality of user push-buttons S1 and S2.
The functionality of the push buttons depends on the CPLD firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0705 System Controller CPLD.
The TE0705 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J14) with two LEDs.
On-board Ethernet MagJack J14 pins are routed to B2B connector JB1 via MDI. The center tap of the Magnetics is not connected to module's B2B connector.
PHY LEDs are not connected directly to the module's B2B connectors as the TE 4 x 5 cm modules have no dedicated PHY LED pins assigned. PHY LEDs are connected to the TE0705 System Controller CPLD, that can route those LEDs to some the module's IO Pins. In that case, the CPLD has to map the PHY LEDs to corresponding module's IO pins.
See documentation of the TE0705 System Controller CPLD to get information of the function of the PHY LEDs.
On the TE0705 there two IDC header available for access to SoM's PL IO-bank pins
J5 and J6 sockets signal routing is done as differential pairs for pins 1-3, 2-4, 5-7, 6-8, hence 4 LVDS pairs are possible on this sockets. The differential pairs are operable with max. VCCIO voltage VIOTB.
IDC header J1 provides access to SoM's PL IO-bank pins, whereby 6 pins (net name: 'MIO10' to 'MIO15') of this header are also routed to the System Controller CPLD.
If Zynq-module is mounted on the TE0705 carrier board, the pins of this header are routed to the corresponding pins of the PS logic of the SoM: MIO0-bank pins MIO0, MIO9-MIO15 are accessible on header J1 and operable with max. VCCIO voltage 3.3V.
An exception here is the 'MIO12'-pin, which is buffered with a Schmitt-Trigger-Buffer with a hystersis of 5.0V.
SoM's PL IO-bank pins are accessible on socket J2. The IO-signals are routed from this socket to B2B-connector JB3 and are only single-ended IOs, hence this signal-pins are not usable as differential pairs. Maximal VCCIO voltage is VIOTB on this socket.
40-Pin-Header J11 and J13 for access to SoM's PL IO-bank-pins on B2B-connectors JB1 and JB2. Operable with fixed (3.3V) or adjustable VCCIO voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).
operable with fixed (3.3V) or adjustable IO-voltage VIOTB (not usable as LVDS pairs, only single-ended IOs).
Power supply with minimum current capability of 3A at 12V for system startup is recommended.
The on-board voltages of the carrier board will be powered up simultaneously after one single power-supply with a nominal voltage of 12V is connected to the power-jack J10.
The PL IO-bank supply voltage FMC_VADJ will be available after the output of the 5.0V-DCDC-converter is active and the pin EN_FMC of the SC-CPLD is asserted.
Figure 3: Power-Up sequence diagram.
On the TE0705 carrier board different VCCIO configurations are selectable by jumper J21 and DIP-switch S3.
The purpose of the jumper and the DIP-switch S3 of the Carrier Board will be explained in the following sections.
There is the possibility to select the module's PL IO-bank's supply voltage VIOTB to fixed adjustable voltages VADJ. Therefore, the jumper J21 has to be set to the position 1, 2-3, to connect the pins 'VIOTB' and 'ADJ'. On position 1-2, 3, the supply voltage VIOTB will be fixed to 3.3V
Table 3 shows the switch-configuration of the DIP-switch S3 to set the voltage VADJ.
Note: The configuration of VADJ depends on the used firmware of the System Controller CPLD. For detailed information, refer to the documentation of the TE0705 System Controller CPLD.
S3-1 (CM1) | S3-2 (CM2) | VADJ Value |
|---|---|---|
OFF | OFF | 1.8V |
OFF | ON | 2.5V |
ON | OFF | 3.3V |
ON | ON | 1.8V (Note: Also SoM's SC-CPLD JTAG-access is enabled, see section JTAG in the documentation of the TE0705 System Controller CPLD.) |
Table 3: Switch S3 positions for fixed values of the VADJ voltage
The TE0705 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the over-current logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).
Additionally, the TE0705 carrier board is equipped with a second mini USB port J7 that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0705 carrier board and the mounted SoM, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.
On the TE0705 carrier board all PL IO-bank's supply voltages of the 4 x 5 SoM (VCCIOA, VCCIOB, VCCIOC, VCCIOD; see 4 x 5 Module Integration Guide) are connected to the VCCIO voltage VIOTB, which is either fixed to 3.3V (J21: 1-2, 3) or selectable with the adjustable supply-voltage VADJ (J21: 1, 2-3). The supply-voltages have following pin assignments on B2B-connectors:
baseboard supply-voltages | baseboard B2B connector-pins | standard assignment of PL IO-bank supply-voltages on TE 4x5 module's B2B connectors | baseboard voltages and signals connected with |
|---|---|---|---|
| VIOTB | JB1-10, JB1-12, JB2-2, JB2-4, JB2-6, JB2-8, JB2-10 | VCCIOA (JM1-9, JM1-11), VCCIOB (JM2-1, JM2-3), VCCIOC (JM2-5), VCCIOD (JM2-7, JM2-9) | VCCIO3 (System Controller CPLD pin 5, 11, 23), J15 VTREF, J11, J13, J2, J5 and J6 VCCIO |
Table 4: baseboard supply-voltage VIOTB.
Note: The corresponding PL IO-voltage supply voltages of the 4 x 5 SoM to the selectable baseboard voltage VIOTB are depending on the mounted 4 x 5 SoM and varying in order of the used model. Refer to SoM's schematic to get information about the specific pin assignment on module's B2B-connectors regarding PL IO-bank supply voltages and to the 4 x 5 Module integration Guide for VCCIO voltage options. |
Following table describes how to configure the baseboard supply-voltages by jumpers:
baseboard supply-voltages vs voltage-levels | VIOTB | USB-VBUS |
|---|---|---|
| 3V3 | J21: 1-2, 3 | - |
| VADJ | J21: 1, 2-3 | - |
| 5V0 intern | - | J9: 1-2, 3 & J19: 1-2 (J20: 1-2: additional decoupling-capacitor 100 µF) |
| Vbus extern | - | J9: 1, 2-3 & J19: open |
Table 5: Configuration of baseboard supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open.
| It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM. |
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | 11.4 | 12.6 | V | 12.0V supply voltage ± 5% |
Storage temperature | -55 | 125 | °C | Lattice MachX02 family data sheet |
| Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
| Vin supply voltage | 11.4 | 12.6 | V | - |
Board size: 170.4 mm × 98 mm. Note that few parts are slightly hanging over the PCB edge, like mini USB jacks (ca. 1.4 mm) and the Ethernet RJ-45 jack (ca 2.2 mm), which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.
Mating height of the module with standard connectors: 8 mm.
PCB thickness: ca. 1.65 mm.
Highest part on the PCB is the Ethernet RJ-45 jack (approximately 17 mm). Please download the step model for exact numbers.
All dimensions are given in millimeters.
Figure 4: Physical dimensions of the TE0705-04 carrier board.
Commercial grade: 0°C to +70°C.
Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Approximately 110 g - Plain board.
| Date | Revision | Notes | PCN | Documentation link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |
Figure 5: Hardware revision number.
Hardware revision number is printed on the PCB board next to the model number separated by the dash.
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-02-09 | Ali Naseri, Jan Kumann | TRM for TE0705-04 | |
| 2017-01-15 | 0.1 | Ali Naseri | Initial document. |
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-10-04 | 04 | |||
| - | 03 | |||
| - | 02 | |||
| - | 01 |