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The Trenz Electronic TE0726 "ZynqBerry" is a industrial-grade Raspberry Pi form-factor compatible FPGA SoM (System on Module) based on Xilinx Zynq-7010 SoC (XC7Z010 System on Chip) with up to 512 MByte DDR3L SDRAM, 4 x USB 2.0 ports, 10/100 Mbit Ethernet port and 16 MByte Flash memory. All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
128 Mbit (16 MByte) 3.0V SPI Flash memory, U5
Common mode filter with ESD protection, D8
Common mode filter with ESD protection, D9
Highly integrated full featured hi-speed USB 2.0 ULPI transceiver, U18
Up on delivery from Trenz Electronic System Controller CPLD is programmed with the standard firmware and FTDI FT2232H EEPROM contains pre-programmed Digilent license needed by Xilinx software tools for JTAG access, all other programmable devices are empty.
The TE0726-03 module has CSI-2 specification compatible serial camera interface routed from Zynq SoC bank 34 to the connector J3.
FPGA Bank | Zynq Pin | Signal Name | Connected To |
---|---|---|---|
34 | M10 | CSI_D0_P | CSI-2 camera connector J3 |
34 | M11 | CSI_D0_N | CSI-2 camera connector J3 |
34 | P13 | CSI_D1_P | CSI-2 camera connector J3 |
34 | P14 | CSI_D1_N | CSI-2 camera connector J3 |
34 | N11 | CSI_C_P | CSI-2 camera connector J3 |
34 | N12 | CSI_C_N | CSI-2 camera connector J3 |
The TE0726-03 module has MIPI Alliance DSI specification compatible serial display interface routed from Zynq SoC bank 35 to the connector J4.
FPGA Bank | Zynq Pin | Signal Name | Connected To |
---|---|---|---|
35 | F13 | DSI_D0_R_N | DSI display connector J4 |
35 | F14 | DSI_D0_R_P | DSI display connector J4 |
35 | F12 | DSI_D1_R_N | DSI display connector J4 |
35 | E13 | DSI_D1_R_P | DSI display connector J4 |
35 | E11 | DSI_C_R_N | DSI display connector J4 |
35 | E12 | DSI_C_R_P | DSI display connector J4 |
See also section FPGA IO Banks Pin Mapping, pins DSI_XA and DSI_XB.
HDMI interface is routed from Zynq SoC bank 34 to the external connector J6 via EMI4192 ESD protector/EMI filters.
FPGA Bank | Zynq Pin | Signal Name | Connected To |
---|---|---|---|
34 | K12 | CEC_B | HDMI connector J6 |
34 | P8 | HDMI_TX0_N | HDMI connector J6 via EMI filter/ESD protector |
34 | P9 | HDMI_TX0_P | HDMI connector J6 via EMI filter/ESD protector |
34 | R10 | HDMI_TX1_N | HDMI connector J6 via EMI filter/ESD protector |
34 | P10 | HDMI_TX1_P | HDMI connector J6 via EMI filter/ESD protector |
34 | R11 | HDMI_TX2_N | HDMI connector J6 via EMI filter/ESD protector |
34 | P11 | HDMI_TX2_P | HDMI connector J6 via EMI filter/ESD protector |
34 | R7 | HDMI_TXC_N | HDMI connector J6 via EMI filter/ESD protector |
34 | R8 | HDMI_TXC_P | HDMI connector J6 via EMI filter/ESD protector |
Pulse-width modulated stereo audio output is routed from Zynq SoC bank 34 to external 3.5mm socket J7.
FPGA Bank | Zynq Pin | Signal Name | Connected To |
---|---|---|---|
34 | N7 | PWM_L | 3.5mm stereo socket J7 |
34 | N8 | PWM_R | 3.5mm stereo socket J7 |
Micro SD memory card connector J9 with detect switch is connected to the Zynq Soc PS MIO bank 500. See also section Default MIO Mapping.
Bank | Zynq Pin | Name | Connected To |
---|---|---|---|
34 | G14 | PUDC | Jumper J14 |
35 | G15 | DSI_XA | System Controller CPLD, pin 16 |
35 | F15 | DSI_XB | System Controller CPLD, pin 17 |
GPIO | Zynq Pin | J8 Pin | GPIO | Zynq Pin | J8 Pin | |
---|---|---|---|---|---|---|
GPIO2 | K15 | 3 | GPIO15 | N13 | 10 | |
GPIO3 | J14 | 5 | GPIO16 | L13 | 36 | |
GPIO4 | H12 | 7 | GPIO17 | G11 | 11 | |
GPIO5 | N14 | 29 | GPIO18 | H11 | 12 | |
GPIO6 | R15 | 31 | GPIO19 | R12 | 35 | |
GPIO7 | L14 | 26 | GPIO20 | M14 | 38 | |
GPIO8 | L15 | 24 | GPIO21 | P15 | 40 | |
GPIO9 | J13 | 21 | GPIO22 | H13 | 15 | |
GPIO19 | H14 | 19 | GPIO23 | J11 | 16 | |
GPIO11 | J15 | 23 | GPIO24 | K11 | 18 | |
GPIO12 | M15 | 32 | GPIO25 | K13 | 22 | |
GPIO13 | R13 | 33 | GPIO26 | L12 | 37 | |
GPIO14 | M12 | 8 | GPIO27 | G12 | 13 |
Bank 500 MIOs
MIO | Function | Notes |
---|---|---|
0 | MIO0_INT | Interrupt signal from I2C MUX. |
1 | SPI0_CS | SPI chip select. |
2 | SPI0_DQ0/M0 | Bi-directional data line 0 |
3 | SPI0_DQ1/M1 | Bi-directional data line 1 |
4 | SPI0_DQ2/M2 | Bi-directional data line 2 |
5 | SPI0_DQ3/M3 | Bi-directional data line 3 |
6 | SPI0_SCK | SPI clock. |
7 | MIO7 | RESETB of USB3320 chip, U18 |
8 | MIO8 | System Controller CPLD pin 28 |
9 | MIO9 | System Controller CPLD pin 29 |
10 | SD_D0 | Serial data 0. |
11 | SD_CMD | Command/Response. |
12 | SD_CLK | Serial clock. |
13 | SD_D1 | Serial data 1. |
14 | SD_D2 | Serial data 2. |
15 | SD_D3 | Serial data 3. |
Bank 501 MIOs
MIO | Function | Notes |
---|---|---|
28 | OTG-DATA4 | ULPI bi-directional data bus. |
29 | OTG-DIR | Data bus direction control signal. |
30 | OTG-STP | Data throttle signal. |
31 | OTG-NXT | Data stream stop. |
32 | OTG-DATA0 | ULPI bi-directional data bus. |
33 | OTG-DATA1 | ULPI bi-directional data bus. |
34 | OTG-DATA2 | ULPI bi-directional data bus. |
35 | OTG-DATA3 | ULPI bi-directional data bus. |
36 | OTG-CLK | ULPI clock. |
37 | OTG-DATA5 | ULPI bi-directional data bus. |
38 | OTG-DATA6 | ULPI bi-directional data bus. |
39 | OTG-DATA7 | ULPI bi-directional data bus. |
48 | MUX_SCL | I2C clock to I2C MUX. |
49 | MUX_SDA | I2C data to/from I2C MUX. |
52 | MIO52 | System Controller CPLD pin 20 |
53 | MIO53 | System Controller CPLD pin 21 |
There are two LEDs on TE0726 module:
LED | Signal Name | Color | CPLD Pin | Notes |
---|---|---|---|---|
D1 | GLED | Green | 5 | CPLD bank 3. |
D2 | RLED | Red | 4 | CPLD bank 3. |
There is a System Controller CPLD chip LCMXO2-256HC from Lattice Semiconductor on-board. Refer to the TE0726 CPLD for more information.
Signal Name | Clock IC | Default Frequency | Destination IC | Pin | Notes |
---|---|---|---|---|---|
PS_CLK | U14 | 33.333333 MHz | U1 | C7 | Zynq SoC system reference clock. |
OSCI | U7 | 12.000000 MHz | U3 | 3 | FT2232H oscillator input. |
CLK24M | U2 | 24 MHz (see also REFSEL0 .. 2) | U18 | 26 | Reference input/output clock, see datasheet. |
CLK25M | U13 | 25.000000 MHz | U2 | 61 | External 25 MHz crystal input. |
The TE0726-03 has on-board SMSC LAN9514 controller featuring USB 2.0 hub and 10/100 Mbit Ethernet controller. USB hub has four downstream ports and one upstream port, fully compliant with Universal Serial Bus Specification Revision 2.0. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible. Upstream port is connected to the SMSC USB3320 hi-speed USB 2.0 ULPI transceiver which has full support for the optional On-The-Go (OTG) protocol.
High-Performance 10/100 Ethernet controller integrated into the same LAN9514 IC is fully compliant with IEEE802.3/802.3u standards, has integrated Ethernet MAC and PHY and supports both 10BASE-T and 100BASE-TX media.
256-byte EEPROM is connected via Microwire to the LAN9514 chip to store MAC address.
The TE0726-03 has on-board high-speed USB 2.0 to UART/FIFO FT2232H controller from FTDI with external connection to micro-USB connector J1. There is also a 256-byte EEPROM wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools.
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content. |
Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I2C multiplexer chip TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are routed as follows:
Channel | Connected To |
---|---|
0 | Connector J8, pin 27 (ID_SDA) and pin 28 (ID_SCL). |
1 | DSI connector J4, pin 12 (DSI_SDA) and pin 11 (DSI_SCL). |
2 | HDMI connector J6, pin 16 (SDA) and pin 15 (SCL). |
3 | CSI-2 camera connector J3, pin 14 (CSI_SDA) and pin 13 (CSI_SCL). |
Each slave channel of TCA9544A has its own dedicated interrupt signal in order for the master to detect an interrupt on the INT output pin that can result from any of the slave devices connected to the INT0-INT3 input pins.
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader.
At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest solution is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load Linux or any other OS image from SD Card.
Xilinx Zynq devices in CLG225 package do not not support SD Card boot directly from ROM bootloader.
At least FSBL must be loaded from on-board SPI Flash, later all boot process can continue from SD Card. The easiest way is to let FSBL to load bitstream and u-boot from SPI Flash, and then let u-boot to load linux or any other OS image from SD Card.
To power-up a module, 5.0V power supply with minimum current capability of 1A is recommended.
TE0726 needs one single power source via micro-USB jack J1. However it is recommended to not use any USB equipment below USB standard 2.0 to power the module. Also two-pin header J5 can be used to provide power source if needed.
There is no specific power-on sequence.
Rail/Bank | Name | Voltage | Notes |
---|---|---|---|
VCCINT | VCCINT | 1.0V | PL internal supply voltage. |
VCCPINT | VCCPINT | 1.0V | PS internal logic supply voltage. |
VCCPLL | VCCPLL | 1.8V | PS PLL supply. |
VCCBATT_0 | VCCBATT_0 | 1.8V | |
VCCAUX | VCCAUX | 1.8V | PL auxiliary supply voltage. |
VCCPAUX | VCCPAUX | 1.8V | PS auxiliary supply voltage. |
VCCADC_0 | VCCADC_0 | 1.8V | |
RSVDVCC1..3 | RSVDVCC1..3 | 3.3V | |
0 | VCCO_0 | 3.3V | Configuration bank. |
34 | VCCO_34 | 3.3V | PL HR I/O bank. |
35 | VCCO_35 | 1.8V | PL HR I/O bank. |
500 | VCC_MIO_500 | 3.3V | PS MIO bank. |
501 | VCC_MIO_501 | 3.3V | PS MIO bank. |
502 | VCCO_DDR_502 | 1.35V | DDR3L SDRAM power-supply. |
TE0726 Variant | Zynq SoC | RAM | Flash | Ethernet | Temperature Range |
---|---|---|---|---|---|
TE0726-03R | XC7Z010-1CLG225C | 128 MByte | 16 MByte | - | Commercial grade |
TE0726-03M | XC7Z010-1CLG225C | 512 MByte | 16 MByte | 10/100 Mbit | Commercial grade |
TE0726-03-07S-1C | XC7Z007S-1CLG225C | 512 MByte | 16 MByte | 10/100 Mbit | Commercial grade |
If TE0726 module is powered by micro-USB connector J1 VBUS pin, which voltage level is controlled by supplying host according to the USB standards and should be 5V, there is not much user can control here if using standard USB equipment. However, user can also power the module by applying voltage to the J5 connector from other external sources. In both cases following maximum voltage ratings apply.
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
Power supply voltage | 2.7 | 6.5 | V | See AP2152SG-13 datasheet. Not applicable if TE0726 module is powered by micro-USB connector J1 as VBUS pin voltage level of 5V is controlled by the supplying side equipment. |
Bank 34 I/O input voltage | -0.4 | VCCO_34 + 0.55 | V | |
Bank 35 I/O input voltage | -0.4 | VCCO_35 + 0.55 | V | |
Storage temperature | -55 | +125 | °C | - |
See also the Xilinx datasheet DS187 for more information about absolute maximum ratings.
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
Power supply voltage | 2.7 | 5.5 | V | See AP2152SG-13 and EN5311QI datasheets. |
Bank 34 I/O input voltage | -0.2 | VCCO_34 + 0.2 | V | |
Bank 35 I/O input voltage | -0.2 | VCCO_35 + 0.2 | V | |
Operating temperature | 0 | 70 | °C | See LAN9514 datasheet. |
The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Module size: 40 mm × 30 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters. Additional sketches, drawings and schematics can be found here.
Variant | Weight in g | Note |
---|---|---|
TE0726-03M | --- | Plain module. |
TE0726-03R | --- | Plain module. |
TE0726-03-07S-1C | --- | Plain module. |
Date | Revision | Notes | PCN Link | Documentation Link |
---|---|---|---|---|
2016-05-06 | 03 | - | - | TE0726-03 |
2016-01-26 | 02 | - | - | TE0726-02 |
- | 01 | - | - |
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
Date | Revision | Contributors | Description |
---|---|---|---|
2017-05-24 | Jan Kumann | Absolute maximum ratings. Layout redesign. | |
2017-05-24 | V.2 | John Hartfiel | Weight. |
2017-05-24 | V.1 | Jan Kumann | Initial version. |