Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0720+TRM for online version of this manual and additional technical documentation of the product.

The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z020 or XC7Z014S) with up to 1 GB of DDR3/L SDRAM, 32MB of SPI flash memory, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. See also Variants Currently in Production section.

Key Features

• Xilinx XC7Z SoC (XC7Z020 or XC7Z014S)
  • Processing system (PS):
    
    • XC7Z020: Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
    • XC7Z014S: Single-core ARM Cortex-A9 MPCore™ with CoreSight™
    • L1 cache: 32 KByte instruction, 32 KByte data per processor
    • L2 cache: Unified 512 KByte
  • Programmable logic (PL): Artix-7 FPGA
    • Programmable logic cells: 85K (XC7Z020), 65K (XC7Z014S)
    • Block RAM: 4.9 MByte (XC7Z020), 3.8 MByte (XC7Z014S)
    • DSP slices:  220 (XC7Z020), 170 (XC7Z014S)
    • Peak DSP performance: 276 GMACs (XC7Z020), 187 GMACs (XC7Z014S)
    • 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
• 54 multiuse I/O (MIO) pins
• 152 High-Range (HR) I/O pins (SelectIO interfaces)
• System Controller CPLD (Lattice LCMXO2-1200HC)
• 1 GByte DDR3/L memory, 2 x 256 Mbit x 16 (32-bit wide)
• 32 MByte Quad SPI Flash memory
• Gigabit Ethernet transceiver PHY (Marvell 88E1512)
• MAC address serial EEPROM with EUI-48™ node identity (11AA02E48)
• Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK)
• 3-axis accelerometer and 3-axis magnetometer (ST Microelectronics LSM303DTR) (Optional!) 
• Real time clock with embedded crystal (Intersil ISL12020M): ±5ppm accuracy
•  Atmel CryptoAuthentication element (Atmel ATSHA204A)
• Up to 32 GByte eMMC, usually 4 GByte, depends on module variant and assembly option
• User LED 1 (Green), user LED 2 (Red), user LED 3 - FPGA DONE (Green)
• On-board high-efficiency DC-DC converters for all voltages used
• Trenz 4 x 5 module socket connectors (3 x Samtec LSHM series connectors)
• Evenly-spread supply pins for good signal integrity
• Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Components and connections marked with dashed lines are optional or may be missing on some module variants, please contact us for additional information.

Main Components

1. Xilinx Zynq XC7Z SoC, U5
2. 4 Gbit DDR3/L SDRAM, U13
3. 4 Gbit DDR3/L SDRAM, U12
4. Low-power RTC with battery backed SRAM, U20
5. 32 MByte Quad SPI Flash memory, U7
6. Red LED (LED1), D5
7. Green LED (LED2), D2
8. System Controller CPLD, U19
9. eMMC NAND Flash, U15
10. 4A high-efficiency PowerSoC DC-DC step-down Converter (1V), U1
11. Green LED (DONE), D4
12. B2B connector Samtec Razor Beam™ LSHM-130, JM3
13. B2B connector Samtec Razor Beam™ LSHM-150, JM1
14. B2B connector Samtec Razor Beam™ LSHM-150, JM2
15. Hi-speed USB 2.0 ULPI transceiver, U18
    
16. Gigabit Ethernet (GbE) transceiver, U8
17. Low-power programmable oscillator @ 52.000000 MHz (OTG-RCLK), U14
18. Low-power programmable oscillator @ 33.333333 MHz (PS-CLK), U6
19. Low-dropout regulator (VBATT), U24
20. DDR termination regulator, U4
21. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.5V), U2
22. Atmel CryptoAuthentication chip, U10
23. 2Kbit UNI/O® serial EEPROM with EUI-48™ node identity, U17
24. Low-power programmable oscillator @ 25.000000 MHz (ETH-CLK), U9
25. 1.5A PowerSoC DC-DC step-down converter with integrated inductor (1.8V), U3
26. 3A PFET load switch with configurable slew rate (3.3V), Q1

Initial Delivery State

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

PL I/O signal connections between Zynq SoC's I/O banks and B2B connectors, 152 HR GPIOs total.

PS MIO bank 500 and 501 signal connections to B2B JM1 connector, 14 PS MIOs total.

For detailed information about the pin-out, please refer to the Pin-out tables. 

JTAG Interface

JTAG access to the Zynq SoC and System Controller CPLD is provided through B2B connector JM2.

System Controller I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Default PS MIO Pin Mapping

Quad SPI Interface

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.

eMMC Interface

Ethernet Interface

The Marvell Alaska 88E1512 (U8) is a physical layer device containing a single Gigabit Ethernet transceiver and three separate major electrical interfaces: MDI interface to copper cable, SERDES/SGMII interface and RGMII interface. RGMII interface is connected to the Zynq SoC PS bank 501 MIO pins, see tables below.

SGMII (SFP copper or fiber) pins are routed to the B2B connector JM3 and MDI pins are routed to the B2B connector JM1 (see table below).

Ethernet PHY to B2B connections

Ethernet PHY to Zynq SoC PS MIO ETH0 connections

USB Interface

Hi-speed USB ULPI PHY is provided by USB3320 from Microchip (U18). The ULPI interface is connected to the Zynq SoC PS USB0 via MIO28..39, bank 501.

USB PHY connection

I2C Interface

On-board I²C devices are connected to the System Controller CPLD which acts as a I²C bus repeater for the Zynq SoC. System Controller CPLD signals X1, X3 and X7 are routed to Zynq SoC bank 34. Exact functionality depends on the System Controller CPLD firmware.

Zynq SoC to System Controller CPLD I²C bus

I²C slave device addresses

Boot Process

By default the TE-0720 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B JM1 connector.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U19) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). The System Controller CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in System Controller CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Also interfaces like JTAG and I²C between the on-board peripherals and to the Zynq SoC are by-passed, forwarded and controlled.

Other tasks of the System Controller CPLD are monitoring of the power-on sequence and to indicate the programming state of the Zynq SoC FPGA.

For more detailed information, refer to the TE0720 System Controller CPLD firmware page.

32 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

eMMC Flash Memory

eMMC NAND Flash (U15) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51 (see also Variants Currently in Production for options). Depending on the module variant, different make and model of eMMC chips are available.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

Ethernet PHY to SC CPLD connections

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).

RTC - Real Time Clock

Temperature compensated Intersil ISL12020M IC is used for Real Time Clock (U20). Battery voltage must be supplied to the module VBAT_IN pin from the carrier board to use battery backed functionality. Battery backed registers can be accessed over I²C bus at slave address of 0x6F. General purpose RAM is at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. 

MAC-Address EEPROM

A Microchip 2Kbit 11AA02E48 serial EEPROM (U17) is connected to the System Controller CPLD pin M14 via single-I/O UNI/O serial interface and contains pre-programmed globally unique 48-bit node address compatible with EUI-48^TM specification. Chip is programmed at the factory with a globally unique node address stored in the upper 1/4 of the memory array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use.

Atmel CryptoAuthentication Chip

The ATSHA204A Atmel CryptoAuthentication^TM chip (U10) is connected to the System Controller CPLD pin N14 via single-wire interface providing various security functions and features such as anti-counterfeiting, firmware/media protection, password validation, secure session key exchanging, secure data storage and more. Refer to the product datasheet for more information.

Oscillators

On-board LEDs

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

 * TBD - To Be Determined soon with reference design setup.

Power Distribution Diagram

Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See also Xilinx datasheet DS187 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0720 module.

NOSEQ input signal

NOSEQ input signal from the carrier board can be used to control output of the two DC-DC converters U1 and U3. It works in conjunction with the System Controller CPLD firmware controlled ON_1V0 and ON_1V8 input signals of the U21 and U25 gate ICs.

Power Rails

¹⁾ In case of module variant of TE0720-03-L1IF which uses Xilinx Zynq XC7Z020-L1CLG484I chip with lower power consumption, power rails named 1.5V and VCCO_DDR_502 voltage is actually 1.35V. To achieve this, a resistor with different value is used for R4 (see schematic of the TE0720-03-L1IF for more information).

Bank Voltages

Board to Board Connectors

Variants Currently in Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

Weight

ca 23 g - Plain module

Revision History

Hardware Revision History

There is no hardware revision number marking on the module.

Document Change History

Date	Revision	Contributors	Description
2017-06-21		Jan Kumann	Initial document.

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