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Overview

Refer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TEBF0808/REV04 for downloadable version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TEBF0808 Carrier Board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes.

Key Features

• Mini-ITX form factor, PC Enclosure
• ATX power supply connector
• Optional 12V standard power plug
• Headers
  • Intel 10-pin HDA Audio
  • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
  • PC-BEEPER
• On-board Power- / Reset-Switches
• 2x Configuration DIP-switches
• 2x Optional 4-wire PWM fan connectors
• PCIe Slot - one PCIe lane (16 lane connector)
• CAN FD Transceiver (10 Pin IDC connector or 6-pin header)
• 4x On-board configuration EEPROMs
• Dual SFP+ Connector (2x1 Cage)
• One Display-Port (single lane)
• One SATA Connector
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• 1x USB3.0 on-board header with two ports
• FMC HPC Slot (FMC_VADJ max. VCCIO)
• FMC Fan
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• All Carrier Board peripherals' I²C-interfaces muxed to MPSoC's I²C-interface on PS bank 503
• Quad programmable PLL clock generator SI5338A
• 2x SMA coaxial connectors for clock signals
• MicroSD- / MMC-Card Socket (bootable)
• 32 Gbit on-board eMMC memory (8 banks a 4 Gbit)
• Two System Controller CPLDs Lattice MachXO2 1200 HC
• One Samtec FireFly (4 GT lanes bidirectional)
• One Samtec FireFly connector for reverse loopback
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
• 20 Pin ARM JTAG Connector (PS JTAG0)
• 3x PMOD connector (GPIO's and I²C interface to SC CPLDs / MPSoC module
• Carrier SC CPLD managing power-up sequence of MPSoC module
• On-board DCDC PowerSoCs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBF0808-04 Block Diagram

Main Components

Figure 2: TEBF0808-04 Carrier Board

1. PMOD connector, P2
2. MicroSD Card socket (on bottom side), J16
3. Display Port socket, J13
4. USB3.0 A 2x , RJ45 1x (stacked), J7
5. SFP+ 2x1 cage, J14
6. PCIe x16 connector (one PCIe lane connected), J11
7. FMC HPC, J5
8. FMC-Fan connector 5V, J19
9. USB3.0 connector, J8
10. PC-BEEPER 4-pin header, J23
11. SMA coaxial connector (SI5338A clock output), J32
12. SMA coaxial connector (clock input to MPSoC module), J33
13. eMMC Card socket, J27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. CAN bus 6-pin header, J29
19. CAN bus 10-pin connector, J24
20. ARM-JTAG  20-pin connector, J30
21. ATX power supply connector, J20
22. 4-Wire PWM fan connector, J35
23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
25. Power Jack 2.1mm 12V, J25
26. 4x DIP-switch, S5
27. Power Button, S1
28. Samtec FireFly Connector  for reverse loopback, J21/J22
29. Samtec FireFly Connector (4 GT lanes bidirectional), J6/J15
30. SATA Header, J31
31. 4-Wire PWM fan connector, J26
32. Programmable on-module PLL I²C interface 10-pin header, J17
33. Reset Button, S2
34. INTEL HDA 9-pin header, J9
35. Intel front panel (PWR/RST/LED) 9-pin header, J10
36. Samtec FireFly Connector J6/J15 I²C interface 3-pin header, J34
37. 4x DIP-switch, S4
38. PMOD connector, P3
39. PMOD connector, P1
40. Battery Holder CR1220, B1

Initial Delivery State

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the I/O's MIOx, MIOx ... MIOx, ... are depending on the base-board peripherals connected to these pins.

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MGT Lanes

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JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

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Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

USB Interface

USB PHY is provided with ...

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U..) ..

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

On-board LEDs

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

Power Distribution Dependencies

regulator dependencies and max. current.

put diagram here...

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence Diagram

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

put diagram here...

Voltage Monitor Circuit

if this circuit is fitted on module, describe it here...

Power Rails

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: ... mm.

• PCB thickness: ... mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

 Put mechanical drawings here...

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History

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Date	Revision	Contributors	Description
		John Hartfiel	-removed weight section update template version
2017-06-08	v.20	John Hartfiel	add revision number and update document change history
2017-05-30	v.1	Jan Kumann	Initial document.
	all	Jan Kumann, John Hartfiel

Disclaimer

Features

• Mini-ITX form factor
• ATX Power supply connector (Important 12V only Supply Required)
• optional 12V Standard Power Plug
• USB3 with USB3 HUB
• Gigabit Ethernet RJ45
• MicroSD Card (bootable)
• eMMC (bootable)
• PCIe slot - one PCIe lane (16 Lane Connector)
• Displayport Single Lane
• One SATA Connector
• FMC HPC Slot (1.8V max VCCIO)
• Dual SFP+
• One Samtec FireFly (4 GT lanes bidir)
• One Samtec FireFly connector for reverse loopback
• Fan connectors, PC Enclosure, FMC Fan
• Intel front panel connector (PWR/RST/LED)
• Intel HDA Audio connector
• CAN FD Transceiver (10 Pin IDC Connector)
• 20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

• PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
• FMC HPC
• Dual SFP+
• RJ45 Gigabit Ethernet
• 2x USB3 Host
• Displayport (Single lane)
• microSD
• Two LED's
• CAN FD (using DB9 to IDC10 Cable)
• One PMOD

PC Front Panel I/O

• Reset Button
• Power Button
• Power LED
• HD LED
• Intel HDA Audio
• One USB2 HS Host port
• One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

TEBF0808-REV2 Component Locations

Table: Board Component Description

TE0808 GT Transceivers

GT Lane Assignment

GT CLK Assignment

TE0808 MIO Assignment

MIO Assignment

TE0808 Si5345 PLL Settings

Recommended/Default settings for the Si5345

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

I2C Buses

List of I2C buses and devices (bus numbers as enumerated by Linux).

To init Si5345 use command

si534x /dev/i2c-13 0x69

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

DIP Switch S4 located close to PCIe slot.

LEDs

Power

ATX Power is supported but special 12V ATX power supply must be used.

System controller RGPIO 

Master CPLD Read

Master CPLD Write

Slave CPLD Read

Slave CPLD Write

PCB Revisions

Revision 02

Known Issues:

• signal SFP1 LOS is not connected (fixed in REV 03)
  
  

Revision 03