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Table of Contents

Overview

Refer to https://wiki.trenz-electronic.de/display/DRAFT/TE0722+TRM for downloadable version of this manual and additional technical documentation of the product.

 

The Trenz Electronic TE0722-02 is a DIPFORTy1 "Soft Propeller" based on the Xilinx Zynq-7000 SoC.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE022-02 block diagram.

Main Components

Figure 2: TE0722-02 PCB top side.

Figure 3: TE0722-02 PCB bottom side.

  1. Xilinx Zynq XC7Z010 or Zynq XC7Z007S SoC, U1
  2. Micro SD card socket with card detect, J8
  3. Red LED, D3
  4. Green LED, D2
  5. Red LED, D6
  6. 20-pin connector placeholder, P1
  7. Red LED, D5
  8. Proximity/ambient light sensor, U4
  9. RGB LED, D4
  10. Red LED, D1
  11. 20-pin connector placeholder, P2
  12. Ultra-low supply-current voltage monitor, U4
  13. 2 x 5-pin connector placeholder, J1
  14. 2 x 5-pin connector placeholder, J2
  15. 2 x 5-pin connector placeholder, J3
  16. 16 MByte QSPI Flash memory, U5
  17. Low-power programmable oscillator @ 33.333333 MHz, U8
  18. 1A PowerSoC DC-DC converter (1.0V), U2
  19. 1A PowerSoC DC-DC converter (1.8V), U3

Initial Delivery State

Storage device name

Content

Notes

Quad SPI Flash

Empty

 

Table 1: .

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

  

High or open

SD Card

Low or ground

QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

I/O Signals

Overview of the PL I/O banks signals routed to the external connectors:

BankTypeConnectorI/O Signal CountVoltageNotes
34HRP183.3P0 - P7
34HRP283.3P24 - P31
34HRP210, 5 LVDS pairs3.3 
34HRJ163.3X2A - X2F
34HRJ223.3 
34HRJ343.3X1A - X1D
35HRP18, 4 LVDS pairs3.3 

Table 3: PL I/O signals overview.

JTAG Interface

JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through J2 connector.

JTAG Signal

J2 Connector Pin

TCK 4
TDI 9
TDO 10
TMS 8

Table 4: JTAG interface signals.

Quad SPI Interface

Quad SPI Flash (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Zynq SoC's MIOSignal NameU5 Pin
1SPI0_CS1
2SPI0_DQ0/MIO25
3SPI0_DQ1/MIO32
4SPI0_DQ2/MIO43
5SPI0_DQ3/MIO57
6SPI0_SCK6

Table 3: Quad SPI interface signals and connections.

SD Card Interface

TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.

Zynq SoC's PinConnected ToSignal Name
MIO0J10-9Card detect switch
MIO10J10-7DAT0
MIO11J10-3CMD
MIO12J10-5CLK
MIO13J10-8DAT1
MIO14J10-1DAT3
MIO15J10-2CD/DAT3

Table 4: SD card socket signals.

I2C Interface

I2C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Zynq SoC's PinConnected ToSignal Name
R13J1-9SDA
P13J1-10SCL

Table 7: Zynq SoC I2C interface.

I2C Interface

I2C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.

Zynq SoC's PinConnected ToSignal Name
R13J1-9SDA
P13J1-10SCL

Table 7: Zynq SoC I2C interface.



Default PS MIO Mapping

MIOFunctionConnector PinNotes
0---
1QSPI-SPI Flash-CS
2QSPI-SPI Flash-DQ0
3QSPI-SPI Flash-DQ1
4QSPI-SPI Flash-DQ2
5QSPI-SPI Flash-DQ3
6QSPI-SPI Flash-SCK
7GPIO-Green LED D2
8---
9---
28SD CARDJ8-5CLK
29SD CARDJ8-3CMD
30SD CARDJ8-7DAT0
31SD CARDJ8-8DAT1
32SD CARDJ8-1DAT2
33SD CARDJ8-2CD/DAT3
36I2C-SCL
37I2C-SDA
39GPIO-Si1143 INT pin
49SD CARDJ8-G4Card detect switch

Table 5: .

 

 

On-board Peripherals

Quad SPI Flash Memory

Proximity and Ambient Light Sensor

Oscillators

On-board LEDs

LEDColorConnected ToDescription and Notes
D1RedLED2, U4 
D2

Green

MIO7, U1User controlled, default OFF (when PS7 has not been booted).
D3

Red

LED1, U4

 
D4RGB

RGB_R, U1

RGB_G, U1

RGB_B, U1

 
D5RedLED3, U4 

D6

Green

DONE, U1

Reflects inverted DONE signal. ON when FPGA is not configured,

OFF as soon as PL configuration is finished.

Table 6: .

Power and Power-On Sequence

Power Consumption

The maximum power consumption of the module mainly depends on the design running on the Zynq SoC's FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It is also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
3.3VTBD*

Table 7: Typical power consumption.

 

 * TBD - To Be Determined.

Power supply with minimum current capability of 1A for system startup is recommended.

Power-On Sequence

... diagram will be here soon ...

Variants Currently in Production

 Module VariantXilinx Zynq SoC

ARM

Cores

PL

Cells

LUTsFlip-FlopsBlock RAM

DSP

Slices

Operating

Temperature

Temperature

Range

TE0722-02IXC7Z010-1CLG225IDual-core28K17,6K35,2K2.1 MBytes80

–40°C to +85°C

Industrial
TE0722-02XC7Z010-1CLG225CDual-core28K17,6K35,2K2.1 MBytes80

0°C to +70°C

Commercial
TE0722-02-07S-1CXC7Z007S-1CLG225CSingle-core23K14,4K28,8K1.8 MBytes66

0°C to +70°C

Commercial

Table 8: Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

-0.53.6

V

Xilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics".

Storage temperature

-40

+85

°C

Silicon Labs Si1141/42/43 datasheet.

Table 9: Module absolute maximum ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
Supply voltage1.143.465 VXilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics".

Table 10: Module recommended operating conditions.

 

Assembly variants for higher storage temperature range are available on request.

Physical Dimensions

 All dimensions are given in millimeters.

 

Figure 4: TE0722-02 physical dimensions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2015-10-2302  TE0722-02
 

01

 

  

Table 11: TE0722 module hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 5: TE0722 module hardware revision number.

Document Change History

Date

Revision

Contributors

Description

Jan Kumann

Initial document.

Table 12: Document change history.

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